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LNA parameters of CC1000
I'm working in modeling the CC1000 ins Verilog-AMS for further simulations with another systems described in Verilog-AMS, System C AMS, etc.
I'm modeling by down-to-top way. I started by the first stage in the receive mode, the LNA block. Some of the parameters I...
Hi, my name is Breno and I'm studying how to implement a transceiver with some parameters. First I would like to know if anyone has a code in Verilog-AMS of a transceiver that can help me.
Thanks,
Breno
verilog ams testbench
Hi, my name is Breno and I am from Brazil, so I apologize about my English.
I am studying verilog AMS to implement an Analog to Digital Converter. My doubt is about how can I simulate an analog module? I tried to simulate some examples given in the page...
rtl compiler set_attr
Hi, my name is Breno and I'm working with RTL Compiler.
The problem is that the new version of Cadence don't support the commands insert_scan and insert_boundary_scan.
To insert the boundary scan, it can still be done using the command build_top_shell of ET. But to insert...
SystemVerilog
Hi, I'm trying to do a random coverage of a serial. For this I'm first trying to do a testbench for a mux 2:1. Actually I've already did a testbench of this, but I'm not getting it right when I try to make it random.
Does anyone know how to do a random testbench for a mux?
Thanks.
Project of Ibias
Hello, how can I project a current source? I have to project an Ibias of 2 uA. I was thinking about projecting a Cascode Current-Sinker Inverter, but is just that simple? I've seen once, some big projects just for Ibias, so I'm not sure about this simple inverter. I've looked...
spice opus
Hello, I'm trying to simulate a differential amplifier in Spice Opus, but I'm having a problem and I don't know how to solve it.
Here is the code:
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Transistor exp_10_SRv2
* input node 7 e 6
* output node 12
* current source --...
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