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Hi, as you can see on the image there is a red area which is between 2 wires. This area is connected to anything. My GND plane is the third one. I did this to prevent to the crosstalk between the 2 signals.
Thank you.
Hi,
I would like to create a ground plane between 2 wires (on the top), i have a layer for the ground and i would like to associate this ground plane on the top to the ground layer.
When i changed the the name of the ground plane (GND) , it dissapears, i thought about a via to change the layer...
Hello,
In my firm we are thinking to buy a software for electrical simulation. We do analog circuit. Our choice are between PROTEUS, LTSPICE, ELDO. Anyone can talk about his experience about theses softwares.
Thank you.
Hi,
I try to understand this programm
----------------------------------------------------------------------------------------------------------------
-- XOR_SIG.VHD
-- May 2001
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC)...
Thank you ads-ee because in a pdf document i have seen other results which are:
After 1 clock cycle a=1;b=2;c=10;d=10;
After 2 clock cycle a=1;b=10;c=10;d=10;
After 3 clock cycle a=10;b=10;c=10;d=10;
But i think it's false here.
Thank you ! But is it correct to say ? :
After 1 clock cycle a=2;b=3;c=10;d=10;
After 2 clock cycle a=3;b=10;c=10;d=10;
After 3 clock cycle a=10;b=10;c=10;d=10;
Thank you !
Hello, I would like to understand this process and what are the values of a,b,c and d steps by steps ?
-----------------------------
if clk'event and clk ='1' then
a <= b;
b <= c;
c <= d;
end if;
-----------------------------
Imagine, we choose a=1, b=2, c=3, d=10.
Thank you !
Hi all!
I would like to create a ferquency_divider i write this code but it doesn't work, if anyone find a error.
Thank you.
-----------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use...
Ok thank you but it's strange that i have a good comportement when the module MAR is independant and a bad comportement when it is assembly with the same stimulus.
This is my MAR.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MAR is
Port ( ld : in STD_LOGIC;
RAZ : in STD_LOGIC;
clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (12 downto 0);
Q : out STD_LOGIC_VECTOR (12 downto 0));
end MAR;
architecture...
I have problem in the simulation. My goal is to see if my microprocessor works, i check if the adress memeory is read by the memory but unfortunately it is not the correct adress in input of the memory.
- - - Updated - - -
I have also this kind of warning
WARNING: Simulation object...
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