Signals and variables in VHDL

[bob2987]

Hi,

I try to understand this programm

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Code VHDL - [expand]
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-- XOR_SIG.VHD
-- May 2001
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
 
 port (A, B, C: in STD_LOGIC;
 X, Y: out STD_LOGIC);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
 SIG:process (A,B,C)
 begin
 D <= A; -- ignored !!
 X <= C xor D;
 D <= B; -- overrides !!
 Y <= C xor D;
 end process;
end SIG_ARCH;
 
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Why this code : D <= A; will be ignored ? And what overrides means ?

**broken link removed**

Thank you.

 

[barry]

You need to study more about VHDL signals and variables. Signals get assigned at the end (and ONLY at the end) of a process; variables get assigned immediately.

 

[K-J]

The assignment on line 17 won't be ignored, it is replaced by the assignment that is a couple lines further down on the process. Signals don't actually update until the process either finishes or his some form of wait statement.

Kevin Jennings

 

[vGoodtimes]

Yes, signals make use of non-blocking assignments (expression is evaluated, but result is not assigned until end of process), while variables make use of blocking assignments (expression is evaluated and result is assigned at that line).

Variables are more commonly used in functions and procedures, but can be used in synthesizable code. Sometimes I see them used as locally defined registers in a clocked process. I like the idea of locally defined signals for registers, but that isn't supported*. I don't like using variables to infer registers because it introduces some order dependence in the code that can be overlooked. I've seen one clocked process where the same variable was used as a register and as combinatorial logic by using the value (register), setting it, then using it again (updated, so combinatorial).

In some simulators, variables result in faster simulations. I tried this out in ISIM (old xilinx simulator) and sadly got a massive speedup using variables. I say "sadly" because it means a developer tradeoff between a consistent style and high-performance sim. Perhaps other simulators can optimize signals better.

I do like using variables in processes for common sub-expressions. eg, if (fifo_wr and not fifo_full) appears in a dozen lines of a process, I'll make a variable "fifo_successful_wr" for it.

Perhaps others can provide their opinions on how/what variables should be used for.

* you can get local signals with a "block" or "if true generate", but I don't see anyone do that.

 

[TrickyDicky]

To the OP: your code contains no variables - what exactly is your question to differentiate the two?
Your question has already been answered by others - it is assigned, it's just overridden. This can be very useful if you want to assign a default value to a signal:

op <= '0';

if set_1 = '1' then
  op <= '1';
end if;

You need to study more about VHDL signals and variables. Signals get assigned at the end (and ONLY at the end) of a process; variables get assigned immediately.

Not at the end - they are assigned when a process suspends. If there is no sensitivity list and no wait-statements are hit - the process will loop foreever in a single delta and a signal will never be assigned (and you'll hang your simulator)

snip

I think you're going a bit OT to have another moan.
And blocking - non-blocking are verilog concepts. They kind of apply to vhdl but are never reffered to as such.
And I use local signals in a generate all the time. No-one uses blocks.

 

[p11]

please someone say me , that i have read somewhere that

signal A, B : integer;
signal C : integer;
signal Y, Z : integer; signal M, N : integer; begin process (A,B,C,M,N) begin M <= A; N <= B; Z <= M + N; M <= C; Y <= M + N; end process;

Signal values are assigned after the process execution
Only the last signal assignment is carried out
•M <= A is overwritten by M <= C;
The intermediate signals have to be added to the sensitivity list, as they are read during process execution.



what does the line " Only the last signal assignment is carried out" mean ?

 

[std_match]

what does the line " Only the last signal assignment is carried out" mean ?

It means that if there are more than one assignment to a signal, only the last one will have effect.
This is just a smart way to describe combinatorial logic, as a sequence instead of complex logic.
The resulting hardware is combinatorial, not a sequence, and it helps if you understand what the synthesis tool actually does.

 

[p11]

so if we want every signal assignment to take place ( not only the last one) then what do i need to do?

 

[std_match]

so if we want every signal assignment to take place ( not only the last one) then what do i need to do?

A process is a sequential description of something that happens in zero time. The signals can only be updated once per execution. All signals are determined by the last assignment in the process.

 

[p11]

begin
process (a)

begin

a<= a+1;
a<= a+2;
a<=a+3;

end process

in this case will all this instructions be executed or only a <= a+3;

sorry , bt am totally confused and needs discussion.plz help.

 

[Dan Mills]

What would it mean for all the 'instructions' to be executed?

You are not really writing a program in the software sense of the word, you are describing hardware, and the hardware you describe within a process block is combinatoric in the absence of either an implied or explicit register operation.
A software program tells a processor what to DO, a HDL description tells the gate array what to BE, the difference is fundamental.

a cannot be assigned to a+1, a+2 and a+3 at the same time (Try and draw a logic diagram if you don't believe me), so VHDL resolves the ambiguity by using the last assignment in the process block (a<=a+3.

Regards, Dan.

 

[std_match]

begin
process (a)

begin

a<= a+1;
a<= a+2;
a<=a+3;

end process

in this case will all this instructions be executed or only a <= a+3;

In your example, the first two assignments have no effect and can be removed.
When more than one assignment is done to a signal, there is normally some surrounding logic that select which assignment will be the last.
Assignments that can't be the last (like the two first in your example) are meaningless.

 

[TrickyDicky]

begin
process (a)

begin

a<= a+1;
a<= a+2;
a<=a+3;

end process

in this case will all this instructions be executed or only a <= a+3;

sorry , bt am totally confused and needs discussion.plz help.

Can I just be the pedant with this code.

This code describes a logic loop. Because the process is sensitive to a, and you assigned a <= a + 3, after each process execution, you kick off another execution on the next delta cycle. Hence you're actually trying to +3 an infinite number of times in 0 time. It's an adder with one input being 3, and the other input being the output of the same adder.

 

[FvM]

The example is also meaningless in total.

Signal a can't be driven from a source outside the process, incrementing a signal in a combinational process can't be mapped to any real hardware.

 

[p11]

ok ok, i have got it , i was thinking it as a software program. it is simply an adder , so all the statements will be executed . i.e 1stly the adder has 2 inputs a ,1 then a, 2 then a, 3 ... so we a+1 output is overwritten by a+2 and then a+3 and hence finally we get a+3. so if

begin
process (A,b,c)

begin

a<= a+1;
b <=a+2;
c<= b+3;

end process;

so here c gives us a+1+2+3 finally instead of only a+3 as given by the above program.

 

[TrickyDicky]

wrong again. C simply becomes b + 3.
Signals dont get assigned their value until after the evaluation of the process.

Lets assume A and B and C = 0 at time 0

After the first evaluation.
A = 1
B = 2 (because A was 0)
C = 3.( because B was 0)

After 2nd
A = 2
B = 3
C = 5.

3rd
A = 3
B = 4
C = 6

You need to think in terms of time for signals - the value of a signal at any given time does not change until the end of the current delta cycle

 

[p11]

ok, but for how many times will it evaluate ?

 

[barry]

ok, but for how many times will it evaluate ?

How much time do you have?

 

[std_match]

ok, but for how many times will it evaluate ?

This is the same situation as when you connect the input of an inverter to it's own output.
The real hardware will be an oscillator and the simulator will get stuck forever in a loop if you don't add a time delay.

 

[p11]

as far as i have understood , vhdl just creates a circuit , i.e there are many adders , subtractors , flipflops etc . vhdl is used to program the interconnects , in order to make a big ckt using these logic blocks. signals are nothing bt the input abd output lines of a logic block in an fpga .


here , below an adder of fpga i used , whose inputs are a, b and output is y .

1)
begin 

y <=  a+b;

end behavioral;

 




2)

begin

y <= a and b;

z <=  a and d ;

end behavioral 







3)
begin

process (a, b)

begin

y <=  a and b;

y <=  a nand b;

end process 

end behavioral;

in the 2nd case it uses 2 adders .


in the 3rd case using process

here the output will give a nand b only as within process for a same event statements are executed sequentially , and signal assignments are done only at the end of the process.


now plz someone explain me , that when we use variables what does that mean in an fpga ?? i mean how does that get synthesized.??