vhdl process values of signals

[bob2987]

Hello, I would like to understand this process and what are the values of a,b,c and d steps by steps ?

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if clk'event and clk ='1' then

a <= b;
b <= c;
c <= d;

end if;

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Imagine, we choose a=1, b=2, c=3, d=10.

Thank you !

 

[TrickyDicky]

This is a simple shift register. After 3 clock cycles, a b c and d will all be 10, assuming d never changes.

 

[bob2987]

This is a simple shift register. After 3 clock cycles, a b c and d will all be 10, assuming d never changes.

Thank you ! But is it correct to say ? :

After 1 clock cycle a=2;b=3;c=10;d=10;
After 2 clock cycle a=3;b=10;c=10;d=10;
After 3 clock cycle a=10;b=10;c=10;d=10;

Thank you !

 

[ads-ee]

Yes, that's exactly what Tricky was inferring.

 

[bob2987]

Thank you ads-ee because in a pdf document i have seen other results which are:

After 1 clock cycle a=1;b=2;c=10;d=10;
After 2 clock cycle a=1;b=10;c=10;d=10;
After 3 clock cycle a=10;b=10;c=10;d=10;

But i think it's false here.

 

[verylsi]

Hi bob, check the authenticity of the pdf.

it will be -
After 1 clock cycle a=2;b=3;c=10;d=10;
After 2 clock cycle a=3;b=10;c=10;d=10;
After 3 clock cycle a=10;b=10;c=10;d=10;

The scenario might be different in case of asynchronous statements where b,c and d are not in the sensitivity list. in that case if d is constant from the beginning i.e. 10 then values of a, b, c and will remain same in simulation.
again sensitivity list does not matter in terms of hardware synthesis.

you can always simulate and check , whenever you have doubt