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Re: delay times
Fmax=1/(micro setup+micro tco+data_delay),though different company has different definition, what you need to do is to understand the hardware knowledge or physical meaning about signals in timing path
vhdl mpeg4
you know no free lunch here, the only way you can get what you need is just to by the IP core,or you have resort to some thesis and book to do it yourself
u use the intantiated primitive modules to assign the output, but actually it just equals to have continuous assignment in this progress, also it have to be the wire type, if you want to have reg type, u have to have a process, just always block, you can resort something else about this topic...
Re: RTL question
using multiple always or process not only make it easy for simulation,but also make it more efficient for synthsis.customly we are inclined to have follows rules when we write rtl codes:1 funtion-related combinational logic in one always or process 2 do not have multiple...
maybe you can use clock setting to get your clock tree in quartus,at first you set an individual clock as a base clock, and then you generate the derived clock from the base clock,good luck
Re: using VHDL (if …elsif …elsif…else sentence ) meet probl
"waitig、"finish"、"failure"、"receive" are states of the finite state machine,but why do you use some of them as the infering condition in the program,it may well be some problems here. as i see, in the diagram of the machine, the...
as i see the component of v2 and v3 is just to constrain the current across the branch(v2,v3), we can have an alternitave circuit diagram to think of the problem, in the alternitave circuits we have three branch circuits to calculate the answer, i here do not calculate it personally,it is just...
i have a course about implemention of general N-port with FC-1 and part of FC-2 according to standard fibre channel protocol, and i have collect many materials about my course, and learn necessary knowledge point about the protocol, but for me it is so complicated to do a good job myself...
Re: CRC calculation problem
you can refer to the papar named "Parallel CRC Realization"
Added after 40 seconds:
you can refer the papar named "Parallel CRC Realization"
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