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bensooraj

Recent content by bensooraj

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Xilinx FPGA BRAM help needed.

No! I dont use the older .coe files! And I need to inititiate it for testing. However I just want to get out of this strange thing :(
- bensooraj
- Post #3
- Feb 20, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Xilinx FPGA BRAM help needed.

Platform : Xilinx Virtex II Pro Board Software : Xilinx ISE I generated a BRAM (Width : 4; Depth : 16) using IP Core Generator and initialised it using a .COE file. 4-bit address mapped to 4 switches on board. 4-bit data mapped to 4 LEDs on board. When I input the binary values (0000 to 1111)...
- bensooraj
- Thread
- Feb 20, 2012
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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