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Xilinx FPGA BRAM help needed.

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bensooraj

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Platform : Xilinx Virtex II Pro Board
Software : Xilinx ISE

I generated a BRAM (Width : 4; Depth : 16) using IP Core Generator and initialised it using a .COE file.

4-bit address mapped to 4 switches on board.
4-bit data mapped to 4 LEDs on board.

When I input the binary values (0000 to 1111) in a sequence(ascending/descending) for initialising the generated BRAM using the .coe file, it is working properly, right data at any given address.

but for a random sequence of 16 4-bit data, the BRAM is not responding with the right data. Any suggestions please. Am I missing out anywhere?
Thanks.
 

shaiko

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The only thing I can think of is that you used the older .CEO instead of the new one.

But if you intend to use it as RAM (and not as ROM) - why do you initiate it ?
 

bensooraj

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No! I dont use the older .coe files!
And I need to inititiate it for testing. However I just want to get out of this strange thing :(
 

mrflibble

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Well, since you think it responds correctly with linear data... Maybe you are forgetting about the delay between putting in the read address and the data appearing on DOUT? By way of test you could do 4 chunks of 4. So 0-3, 4-7, 8-12 , 13-15 and randomly shuffle those 4 chunks, put them in your .coe. And then see if you recognize the pattern. Or just do a proper testbench, but the 4x4 random shuffle is something you can do real quick with what you have right now. My guess would be that you're forgetting about the delay between asserting address and the data appearing at the output.
 

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