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Hi everyone,
I am using Calibre to check DRC and LVS of my layout. Unlike the Assura which seems straightforward, I am having hard times understanding DRC errors reported by Calibre. I was wondering if there is any helpful document or video in this regard? Thanks in advance.
How to define port in cadence which has a impedance value that is frequency dependent
Hi Everyone,
I am trying to use a port with complex value as a output termination in SP simulation of cadence. For example output port impedance value is 1/(2*pi*freq*C) which is also frequency dependent. Is...
Hello all,
I am developing a piece of code In Hspice that performs a kind of optimization task. The code includes certain parameters (m and w values) that keep changing constantly so as to satisfy the desired goals.
However, I’d like to introduce two constraints into the problem in order to...
Re: Simulink cosimulation error
Thank you very much for your help BradtheRad,
what do you mean?plz clarify what you mean Running what simulink or matlab+I don't think so I did it
Hi every body,
I was trying to simulate my verilog code in Matlab/Simulink using HDL Verifier Toolbox,but I just run into this error and I don't know how to handle it.
Error reported by S-function 'shdlcosim' in 'untitled/HK_Mash_1_1_1/S-Function':
Handshaking with the server failed - Server...
Hello everyone
I Had designed Analog Circuit and now in order to test it,I wanna save data in excel format during simulation and import it into Matlab,I don't know whether in this Circumstance "MatlabSinkF" block of Ads will be useful or not, I Also tested "TimedataWrite" block but it was of no...
We know known the PLL output is Sin(Φout) where Φout=ωout*t+Θ(t),for stability and calculation of the PLL loop I have to find transfer function of Φout(s)/ Φin(s). The Problem is how can I Take Φout from Sin( Φout) in Matlab simulink?
Iam looking for something like arcsin() function but as...
thx dear albbg for you reply
actually i don't wanna calculate the capacitance respect to frequency I have dc analysis and I wanna calculate the output capacitance, in Hspice there is a command for this purpose ".option captab".
Hi every body
I wanna calculate effective capacitance at output node of my designed circuit. I am using ADS 2013 version of software.
Does ADS have any option to calculate it automatically or should i write an equation for it?
thx for you helps
And still 1 thing remains, I can not export the output in VHDL o Verilog Or block diagram format to Import Automatically to other software such as Advanced design system.
thx std_match it was very useful, it helped me alot
by the way, if you already used it,can you tell me that how much should I relay on the answers, I mean does the software has any bug resulting in a wrong answer?
thx for reply dear TrickyDicky
well I don't think so as far as I know at least in ISE we can export the design for automatic lay-out and ASIC application so the software must be able to generate multi level logic gate for lay-out, I don't know whether Quartus supports this feature as ISE does.
well I know what you mean but as a matter of fact in next step I have to Implement Transistor level of my digital circuit in ADS Software and simulated the whole Analog and digital parts together, so I need the optimized version of my digital circuit Individually.
How to Import whole the truth table into Quartus and automatically Optimize it
Hi every one
I had designed a Combinational circuit in Quartus II 13.0 but it was not optimized as the number of input variables were so many I couldn't simplify it using Karnaugh Maps ,so I decided to draw whole...
I have TSMC .18 design kit which is supported by ADS 2009 I did what had been Instructed in order to be capable of using it in ADS 2013 but at the end I run into this error:
Warning(s) reported:
Conversion Error: translating 'TSMC_CM018RF_DIODE' to cell 'TSMC_CM018RF_DIODE' in library...
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