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Recent content by asicganesh

  1. A

    Can differential pads swapped while routing?

    Can differential pads swapped while routing? If so will there be a negation introduced logically due to the swap?
  2. A

    hold checks on half cycle paths

    How PT does hold check for half cycle paths?
  3. A

    why lec performed at various steps

    LEC can be performed both on hierarchical netlist and flat netlist.. Equivalence check is done to check whether netlist (after synthesis optimisation, post cts, post route) is logically equivalent to golden RTL or netlist..
  4. A

    PT missing clock definitions

    How to check in PT missing clock definitions and unregistered flops? Say I have 200 clocks in my design and I miss to define a clock.. how can we figure unregistered flops?
  5. A

    In PT What is the difference between set_disable_timing and set_false_path?

    In PT What is the difference between set_disable_timing and set_false_path constraint? They both look similar? Is there any specific diff?
  6. A

    Primetime Tips to read timing reports

    I am new to PT.. I am reading PTUGs from SOLD.. Are there any good material on "how to Read PT timing reports".. Tips for quick analysis on violations..
  7. A

    Analyse setup violation using PTSI

    Can anybody help analysing why the setup slack is violated in the report below **************************************** Report : timing -path_type full -delay_type max -max_paths 1 Design : f781715 Version: D-2010.06-SP3 Date : Thu Dec 16 10:43:22 2010...
  8. A

    Gate level simulation

    You can use write_sdf to generate sdf file from your dc_shell itself
  9. A

    Issue with Estimating asic gate count using DC

    You can download the technology library from the fab websites.. try tsmc 65nm library
  10. A

    Verilog Newbie Question: Please Help

    Try this should work input [3:0] d; input clk, rst; output [3:0] q; reg [3:0] hold; always @(posedge clk or posedge rst) begin if (rst) hold <= 0; else hold <= d >> 1; end end assign q = hold;
  11. A

    Clock Phase synchronisation

    Can we phase synchronize two out of phase clocks using RTL code. If so can anyone share me the design approach.
  12. A

    Verilog Compilation problem in module instantiation

    You can't port map this way while instantiating.. .pguclks18 ("ckucsigd[24], ckucsigd[23], ckucsigd[22] ") this will port map it to a string... hence the problem.. Use this way .pguclks18 (ckucsigd[24:22]) This will solve the case..
  13. A

    How to generate sdf using max & min libs so sdf will consists of corresponding delays

    Generation of sdf use write_sdf command in DC to generate SDF file
  14. A

    modes in which STA is performed using Primetime

    scan mode sta What are the various modes in which STA is performed using Primetime. Added after 54 minutes: I mean OCV, PVT are different modes right.. If so then do we generate timing reports in each mode (like with OCV, with PVT). What all analysis are to be made while doing STA.
  15. A

    how to do post simulation with ncverilog?

    You need SDF + Synthesised netlist I hope you have the synthesised netlist. Normally in DC you can generate sdf using write_sdf command.. Mostly a similar instruction should be in RC also.. cross check..
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