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Recent content by asic_ant

  1. asic_ant

    Info about high order sigma delta modulator design

    Sigma Delta paper from IEEE are best, i think
  2. asic_ant

    The relationship between the pole freq and settling time of an OPA

    who has the matlab code to determine the relationship between the pole freq and settling time of an OPA, or any book about that? thank you!!!!!!
  3. asic_ant

    ADC INL and DNL plots

    adc threshold error dnl inl where is the script at MAXIM?
  4. asic_ant

    The pros and cons of various OPA architectures

    OPA i think Gray's book is excellent, read it, it will be great helpful
  5. asic_ant

    Hspice error:internal timestep too small in transient...

    interal timestep too small I often encounter such error. How to deal with it usually?
  6. asic_ant

    Looking for papers about clock in pipeline ADC

    please, anyone know about the clk in pipelined adc? or any paper or book about it ?
  7. asic_ant

    Looking for good references on DLL

    Re: DLL Hi, You topic happened to be my graduation design,but pity I still learn little about it. Here are some documents I think is helpful. Hope you'll benefit too! :D
  8. asic_ant

    Question about an OP-amp model...

    It is an OP model from ahdlLib in Cadence. Why there is a "Vref" pin? And how to use it?
  9. asic_ant

    Where can I get basic information about IC layout?

    Layout basic Info You just simply run the search engine top right corner in the topic lists page and will get lots of topics you interested!
  10. asic_ant

    Need help for an integrator design!

    Still wandering what if the OP's GBW is small than the clock frequency,now that we don't mean to amplify it?
  11. asic_ant

    What's the operating Points regions stand for? (in Spectre)

    When I use HSPICE,it direct indicate the "saturation","cut off","linear". But when come to spectre it is region 1,2,3 Then what are they stand for respectively?
  12. asic_ant

    A question about MOS capacitances

    These are all parasitic capacitances in the real physical chips. Just think about the characteristic of capacitance: if the voltage applyed changes,the amount of charge will changes. Then on the opposite ,if the amount of charge will change with the applied voltage there is a equivalent capacitance.
  13. asic_ant

    Need help for an integrator design!

    The schemetic is attached below. The aim is as follows:for a given period clock signal with any duty cycle,the Integrator will translate it into DC(with little ripple) voltage proportional to the period.(I'm not sure is it the so called frequency-to-voltage converter). Besides,the clock...
  14. asic_ant

    How to carry out the zero/ploe analysis?

    In Allen's book he used a lot, but I just can't understand...
  15. asic_ant

    Evaluating stability in Opamp of integrator

    OPAMP OF integrator I have the same question. Any good ideas or papaers to refer?

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