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Recent content by ash72

  1. A

    A request must be followed by a grant (in the next cycle)

    The spec "A request must be followed by a grant (in the next cycle)". I was given a solution for this spec using VHDL assert, as follows: prev_req <= req when rising_edge(clk); assert_grant_follows_request : process(clk, reset) begin if rising_edge(clk) and reset = '0' then assert...
    • ash72
    • Thread
    • Replies: 0
    • Forum: VHDL
  2. A

    A grant must at some time have been preceded by a request

    The spec : "A grant must at some time have been preceded by a request". In order to write an assertion for this spec, I was given a solution in VHDL, as follows: past_req <= req or past_req when rising_edge(clk); assert_grant_follows_request : process(clk, reset) begin if rising_edge(clk) and...
    • ash72
    • Thread
    • Replies: 0
    • Forum: VHDL
  3. A

    VHDL Process sensitivity list

    Yep, once I initialized all the signals, the process started showing correct behavior. Thanks very much. But I find this behavior very non-intuitive. Thanks. 1639680479 Yes. That was by design to see that B goes to 'X' because of multiple drivers. Thanks for your input.
  4. A

    VHDL Process sensitivity list

    Folks, I am perplexed with VHDL behavior in the following example. It's an EDA playground link, so you can simulate it yourself. library IEEE; use IEEE.Std_logic_1164.all; use std.textio.all; entity E1_TB is end entity E1_TB; architecture BENCH of E1_TB is signal A : Std_logic; signal B ...
  5. A

    Type attribute for enum types in VHDL

    Makes sense. My choice. Thanks very much.
  6. A

    Type attribute for enum types in VHDL

    Thanks much for the pointer to LRM. There is only one paragraph in LRM that talks about encoded values of the enumeration literals. But it says that the numeric values associated are always in ascending range - 0 to N. So, 'Left and 'Low will still result in the same value. Maybe I am missing...
  7. A

    Type attribute for enum types in VHDL

    VHDL question: Assume you have an enum type as follows type color is (R, G, B); Type attribute color'left will give "R". And color'low will also give "R". In such a case will 'left and 'low ever produce different result? If no, then what's the use of these two different attributes for enum type?
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    Synthesis of Integer in Verilog

    Hello, I understand that it's not a good idea to use integers in RTL that is to be synthesized. In the following code, it will generate 32 bit incrementor. But my question is on the continuous assignment. integer I; always @(posedge Clock) if ( Reset || (I == 255) ) I <= 0; else I <= I + 1...
  9. A

    How to write a 'req' before 'ack' systemverilog assertion?

    I am not able to write an assertion for the following spec. $rose(req) must not arrive more than 3 times before $rose(ack) arrives. The $rose(ack) should arrive within 16 clocks. Help!!! Thanks much.
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