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VHDL Process sensitivity list

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ash72

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Folks,
I am perplexed with VHDL behavior in the following example. It's an EDA playground link, so you can simulate it yourself.

Code:
library IEEE; 
use IEEE.Std_logic_1164.all;
use std.textio.all;

entity E1_TB is
end entity E1_TB;

architecture BENCH of E1_TB is 
signal A : Std_logic;
signal B : Std_logic;
signal C : Std_logic;
  
begin 

  process (A, B, C)
  variable var2 : line;
  begin

    
    write(var2, string'("ENTER: At Time = "));
    write(var2, now);
    write(var2, string'(" INPUT  = "));
    write(var2, A);
    write(var2, B);
    write(var2, C);
    writeline(output, var2);

    C <= B after 4 NS;
    B <= A after 10 ns;
    
      write(var2, string'("EXIT: At Time = "));
      write(var2, now);
      write(var2, string'(" iOUT1  = "));
      write(var2, A);
      write(var2, B);
      write(var2, C);
      writeline(output,var2);
  end process;
  
  Stim: process
  begin 
    wait for 1 ns;
    B <= '0'; 
    wait for 25 NS;
    B <= '1';
    wait;
  end process;  
end architecture;

https://www.edaplayground.com/x/Qx_J

My question is why doesn't the process enter when signal 'B' changes in its sensitivity list? The simulation only shows the time 0 uninitialized values of signals in it's sensitivity list. Tried both on Questa and VCS and the same answer.

Thanks for any clarification you can provide.
 
Last edited by a moderator:

Solution
Did you try initializing your signals? You should.
Yep, once I initialized all the signals, the process started showing correct behavior. Thanks very much. But I find this behavior very non-intuitive. Thanks.
--- Updated ---

Signal B has multiple drivers. No useful hardware description.
Yes. That was by design to see that B goes to 'X' because of multiple drivers. Thanks for your input.

ash72

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Did you try initializing your signals? You should.
Yep, once I initialized all the signals, the process started showing correct behavior. Thanks very much. But I find this behavior very non-intuitive. Thanks.
--- Updated ---

Signal B has multiple drivers. No useful hardware description.
Yes. That was by design to see that B goes to 'X' because of multiple drivers. Thanks for your input.
 

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barry

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Yep, once I initialized all the signals, the process started showing correct behavior. Thanks very much. But I find this behavior very non-intuitive. Thanks.
--- Updated ---


Yes. That was by design to see that B goes to 'X' because of multiple drivers. Thanks for your input.
Initializing signals SHOULD be intuitive. You can't start from an unknown condition and expect good results. If I dropped you in an unknown place, could you find your way home?
 
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