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I was browsing through delta-sigma modulaotrs for DACs. I have the following understanding. Can someone explain/correct me if I am right on wrong
1. The integrator which is a linear system in itself in itself makes the input to the quantizer linear,
2. The Quantizer is a non linear block...
Lets talk on a sine wave case. Lets say I am clipping on both the positive and negative peaks. Can you please explain me how this clipping brings out Odd harmonics in say 1K tone.
I do know clipping leads to Harmonics. But it would be great if I can get to know further information on that (possibly Math). could not find that anywhere.
I know we cannot use the force/release statements directly in an UVM run phase because of the interface based communication between TB and DUT.
In case I need to force a pin A in the DUT to logic 1, How can I go about it ?
I could not find any source to get this info.
Thanks ads_ee.
In case of generate statement, I think the compiler creates instatantiates/creates logic as asked for. But the parameter pNUM_CHAN is not getting synthesized. Its the bus that is getting created right.
So, based on that, if the Parameter as I have asked for is synthesizable...
Hello People.
I have a parameter to a module. I have used parameters for but widths and stuff usually. But I am in a different need now.
I am using a FSM which is based on a counter. I am trying to control one of the state changes based on the comparison between count and the value specified...
Thanks Barry. This means out of the whole frequency band, we can choose the bands required by us and filter the rest. Two band passes towards lower frequency and One high pass?
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I was mentioning as an example
A general Question on BiQuad filters.
I come across the term 3 band Bi quad filters. THis has three Biquads cascaded. So, does the term mean that we can have three band of frequencies suppressed/filtered when we use this?
Imagine I have a single driver in the board that has to drive multiple inputs.
We usually buffer the inputs to the input pins of the loads. I know that the drive strength is the one that limits the amount of inputs a driver can drive. But I want to know how can I quantify the no of loads that...
I have a shift register with an asynchronous reset to convert serial to parallel data. All that I do is to shift data through it and decode the data to get the address to be read/written to in an efuse.
I have a simple question. Consider, I disconnect the power supply to the flops. THis would...
how can I calculate the read SNM of the 10T sram used in thebook?
normally i can make a DC sweep on one of the storage nodes and plot the change in case of reading in a 6T sram.. but how can I do for the 10T sram as shown in the thread given above?
Hello friends,
I am currently working on sub-thresold sram design for my thesis. I do not find any recent papers on this topic. I just want to know whats the scope of research on this field.
I have been working for a new design for the past 2 months, but nothing satisfactorey is up. Also, I...
Hello Friends,
I just want some suggestion on what kind of project can I start with to understand the ASIC design flow completely.. Please suggest some ideas on how to go about it.
Thanks
Arun
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