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Recent content by arunjatti

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    Process for writing linker file /scatter file for ARM7

    scatter file Hi all, I'm trying to write a linker file for an ARM7 processor. i.e i want to generate elf/hex file , for it to be used by the ARM processor in SOC. what is the process to write a linker file (*.ld file). I have some prewritten linker file but when i'm using this file for my ARM...
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    Regardin clock divider virtex 2 pro xcv30

    Hi all, Im using a clock divider in virtex 2p , im able to check the clock when implemented in divider module .i.e input is 100Mhz clock output is 1hz clock , but this 1hz clock when im giving to any other module it is showing some prob with skew ettc warning and output is not seen .... how...
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    Do we need to simulate post synthesis verilog file ??

    isdf verilog hello all, Thank you for your responses, Im in the ASIC, the prob is with .v file generated with SNPS DC , I want to simulate the file to check the functionality of the design after being mapped to 180 nm library, I took the same .v file and simulated in Xilinx , but it is not...
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    Do we need to simulate post synthesis verilog file ??

    synthesis in verilog in xilinx Do we need to simulate post synthesis verilog file ?? If so how ??? In which tool we should simulate this , cos when Im simulating the .V file in Xilinx it is showing errors ?? In Xilinx only do we need to add any library related to Design compiler Thanks in...
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    Regardin post synthesis simulation

    Hi all, I got a verilog file after post synthesis using Synopsys DC, then Im simulating the file using Xilinx using test bench waveform, but it is not simulating , can any one help m e in the regard like Is it required to simulate the verilog file ? If req in which tool i should simulate thanks...
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    Please help Regarding Post route and placement simulation

    at 703.065 ns(3): Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; Expected := 0.192 ns; Observed := 0.061 ns; At : 703.065 ns at 703.077 ns(3): Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; Expected := 0.192 ns; Observed := 0.056 ns; At : 703.077 ns at 703.112...
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    Regarding Library files for Synopsys DC and Cadence SOC

    Should we use the same library file s for Synopsys Dc and Cadence so........ease help me in this regard ....where we can get this files
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    Please help urgent !!Regarding post route simulation

    Hi echo, Thankyou very much, i got it
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    Please help urgent !!Regarding post route simulation

    hi all, I'm running a post route simulation, but i hve glitches in my output , how to recover from it ,please help its urgent
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    Why ICs color is black?

    Re: Why IC are black? IC's are black coz to radiate the heat generated inthe chip
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    what is hot-topic in digital design now?

    I think the hot topic in digital design is soc (system-on-chip) and noc(network-on-chip) ..lot of research is going on in this area...
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    Doies any one have synopsys dc tutorial (not sold)

    I want synopsys dc tutorial and ASIC DESIgn M.J.SMITH can any one give me a link
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