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Recent content by arun2011

  1. A

    Substrate Contacts of NMOS and PMOS connected in opposite direction?

    NMOS will be formed in the p-substrate and PMOS will be formed inside the N-well (in a normal N-well process). Bulk which is the fourth terminal of the transistor should be connected in such a way that the S/D terminal and Bulk terminal must be reverse biased , hence they are connected in...
  2. A

    Finger Gate Techniques

    by fingering of transistor we can reduce the drain capacitance & gate resistance...
  3. A

    cross-coupled common centroid transistors layout matching

    for your 1st questn i would suggest the following pattern ABCCBA CABBAC ABCCBA for 2nd questn watevr you suggested is fine......
  4. A

    [SOLVED] How could I draw 45 degree path in virtuoso?

    For each technology there is a minimum grid specified in the PDK, I think you might have set the grid to that minimum value(you can change this by changing the display settings by pressing key 'e') and you are placing the path not in the grid.Place the path exactly on the grid dots your DRC will...
  5. A

    Cut poly in TSMC 28nm

    I think it has got something to do with double pattern lithography.
  6. A

    Confused about the Role of N+ and P+ Guard Ring

    A P+ ring in psub is simply a superior ohmic connection, ties the region together and to some current-return point. It also creates a highly doped region which will not invert even if the substrate does, eliminating surface conduction (field NMOS being susceptible to mobile ion and radiation...
  7. A

    importing gds to virtuoso LE

    hi all I am having a gdsII file from a virtuoso LE i want to open and do the drc and lvs of it from another PC what are the required files and please tel the procedure.... regards arun
  8. A

    current mirror matching

    Hi Joannes Yes, 20 to 1 ratio is a problem...but in your pattern a lot of area will be wasted and also where is the centroid and symmetry in this pattern...please explain ..
  9. A

    current mirror matching

    If M1=15, M2=300 & D is dummy interdigitation can be done as D(20*M2)M1(20*M2)M1(20*M2)M1(20*M2)M1(20*M2)M1(20*M2)M1(20*M2)M1(20*M2)M1M1(M2*20)M1(M2*20)M1(M2*20)M1(M2*20)M1(M2*20)M1(M2*20)M1(M2*20)M1 But this will increase horz area...try using commn centroid, so that it will be a compact one..
  10. A

    Common centroid Better Matching for M1 9 fingers and M2 fingers

    if u want to share u can use this DABBABABBAD DBAABABAABD Regards arun ---------- Post added at 18:40 ---------- Previous post was at 18:37 ---------- i think its better don't go for sharing, it will increase stress due to STI
  11. A

    Common centroid Better Matching for M1 9 fingers and M2 fingers

    D B A B A B A B A B D D A B A B A B A B A D I think this will provide better matching, here D is the dummy transistors and A & B are the transistors 2 be matched
  12. A

    gds 2 and fabrication

    Hi, Thanks for your reply , I ll go thro' the document and ll surely get back to you. Thanks & Regards Arun
  13. A

    About Lacthup remedies

    Latch up will prevent the lateral entry of minority carriers by forming a reverse biased pn jun.
  14. A

    gds 2 and fabrication

    Hi Thanks for your reply, its very helpful. So from what you said and what i studied i am just concluding how our gds2 will be used for fabrication, if i am wrong please correct it. Our layout in gds2 format will be first printed into the mask(photo mask in case of photolithography),(how it is...
  15. A

    gds 2 and fabrication

    Hi all can anyone explain how our layout output(gds2) is used in chip fabrication process, wat i understood is our gds2 file is used to make layout on photomask, and it will b used to project into wafer coated with photoresist..is it correct..plz explain the detailed process. Regards Arun
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