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the latch is level sensitive. so there is an arc from d to q in latch when en =1. the flop is edge sensitive so there is nothing like d-to-q. it is depended on the clock. So you have clock to q.
there will be an arc for every input to output such the input transition causes an output...
You have to go through some basic exercise for selecting slew and load. It has to be done per Vt type of the standard cell at each PVT condition.
a) minimum slew: Take the fastest inverter(highest Drive) loaded by the smallest drive inverter with some approx. wireload. The transition time at the...
no this is not a latch. You are basically feeding the output of DFF to a Mux whose output is coming back to flop. This will create an internal timing loop but it is not a latch.
SPEF is standard so all the tools will print the location of pins/ports. It will be part CONN portion of the spef file. the numbers of coupling caps are different depending on how the tool is breaking up the wires into pieces to estimate the total capacitance. You can really find out the caps on...
double patterning is a fabrication processing step to print the features on the silicon properly. due to reduction in the feature sizes on the chip ( like poly length, metal widths etc), it is difficult to print them properly due to wavelenght of the light waves used for printing them. it...
Most of the clock gaters are designed to keep the output clock to VSS when the enable signal is 0. You can do the opposite as well but it is not common. the negative latch is required because you want the output clock to 0 when the clock gater is off.
the spice netlist is extracted with the power_extract meaning that the VDD and VSS are extracted. then the tool goes and runs simulations to estimate how much cap is offered by the VDD/VSS at the chip. if the metal cap + device cap on the vDD network is XfF. Then if you place five of these cells...
No the frequency change will not impact coupling effects. But as you changing the frequency, i am assuming that transition rates of the clock edges will also change. the transition rates will impact the coupling effects because rise/fall times of the clocks will effect the coupling.
for hold fixing down sizing is the correct way of doing it. this will safe power in the design because downsized cells have lower power. the down side is that they have more timing variation apart from max_tran violations.
I am assuming that the .lib is the timing library. You dont need to convert into .db as the cadence tools will be able to read .lib as it is. .db is a binary database which is supported by synopsys tools. Now these things are all standards. the only reason people use .db is to save disk space or...
can you explain the context of the picture attached in the email. the clock cells are designed for equal rise/fall times in the library. So there will be no pulse narrowing so a clock design. this will only happen only when the transitions are not reasonable. Most of the clock trees are...
The .spf file will contain only the parasitic's for metal/poly. That is the static capacitance associated with the pin. when you running the simulation, the Cgs,Cgd are all voltage dependent values. So you have to run the simulation by integrating the current that is going into the pin for PWL...
is you see the design the input B=0 so there should ideally be no change in the output. But due to charge sharing, there is blip in the vout which is defined as delta vout. The amount of vout drop will depend on the how much is charge sharing is. in simple turns Vtn determines in which region of...
you should do hand calculations to see how much inductance is there between to wires in a design( any standard physics book will have the method). It will be very small. The only place where inductance is extracted when the designer is actually try to make an inductor for RF applications. These...
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