Inverter/Buffer Based Clock Pulse Width

[promach]

I have questions on why we calculate the pulse width using the formula given in https://vlsibasic.blogspot.my/2015/09/min-pulse-width.html . I do not understand how high or low pulse width are calculated.

Besides, from the attachment, why is there Clock Pulse Width Degradation Effect if using clock buffer or inverter chain ? Due to wire RC effect? Why is the high pulse width getting narrower and narrower ?

 

[ThisIsNotSam]

This is simple rise and fall unbalancing, apparently. If all your buffers are able to rise fast, but can't do the same for fall, your clock will get distorted.

 

[artmalik]

can you explain the context of the picture attached in the email. the clock cells are designed for equal rise/fall times in the library. So there will be no pulse narrowing so a clock design. this will only happen only when the transitions are not reasonable. Most of the clock trees are analysed with spice so the inherent numerical in inaccuracies are the main cause of the difference.

 

[MattZ]

CK cells are designed for better rise/fall delay balance, not be exactly the same, no matter the transition. But yes, big transition will make the case even worse.