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Recent content by arpan_sen

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    How to determine the gate delay in terms of input slew and output capacitance

    Gate Delay of a CMOS Inverter = some_function(Input Slew Rate, Output Load Capacitance); I am trying to understand how the gate delay is related to the input slew and output capacitance using mathematical equations. If you could please help me out and/or provide some links/books/papers that...
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    Gate Delay of CMOS Inverter in terms of Input Slew and Output Capacitance

    Gate Delay of a CMOS Inverter = some_function(Input Slew Rate, Output Load Capacitance); I am trying to understand how the gate delay is related to the input slew and output capacitance using mathematical equations. If you could please help me out and/or provide some links/books/papers that...
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    Pointers on levelized code

    Hi All, Any pointers on levelized code algorithm? Regards
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    Need tutorial material on Debussy

    debussy tutorial Hi All, I am new to RTL Debug and have come to know that Debussy is one of the better tools in this area. I would like to get hold of some tutorial documents on Debussy and also other tools that may be used for this purpose. Regards
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    What is a glitch and how to if an equation has a glitch?

    Re: Glich Hi, Looking at an equation you cannot say if that glitches or not. Say you are modelling a latch, and both data and enable change simultaneosuly, the latter being caused by a glitch. This would cause an incorrect behaviour from the circuit's point of view, although the equation as...
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    Looking for paper on BDD and its use in simulation/synthesis

    BDD Anyone on good articles on BDD and the usage in simulation/synthesis etc.? Any help appreciated.
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    Looking for documents on Clock Tree Design theory

    clock tree design Is there any specific text that discusses the Steiner Tree apart from the docs that comes with the s/w tools? Clock Routing, Global Routing etc.
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    which is the best backend book

    VLSI Physical Design Automation is an excellent book. Covers a lot of backend issues and the explanation is crisp and clear.
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    What and why is clock synthesis important?

    On the same lines, I want to know if we have anyone in the group who can lead us to some known algorithms for clock tree routing? I hear that Steiner tree algorithms are quite popular. Thanks in advance.
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    Books for Beginers in [VHDL or Verilog]

    I think the book by Samir Palnitkar is a very good one for begineers in verilog. For VHDL, you may want a hand at Jairam Bhaskar's book. Also check out the book on Logic Synthesis in Verilog by Bhasker.
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    Assertions mechanism between various languages

    Assertions Hi, I believe assertion mechanism between vhdl and systemverilog differ considerably. I wanted to know if PSL or for that matter any other do has the same kind of features assorted. Thanks. #Use proper forum for posting. (Topic moved from Ebook upload/download)# Marie65
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    What's the best tool for verification?

    Do we have anyone in the group who can give some sort of a comparative analysis between the several verification strategies that are on in the industry. I see Vera, SpecMan, SystemVerilog and Jeda all competing in the same space.
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