Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
xds510 clone schematic
Hi,
There seems to be cheap alternative to the 510. Look here:
https://www.olimex.com/dev/tms320-jtag.html
Does anyone have experience with this device ?
Did those tricks lots of times in telecom fpga's
16Mhz + 75 = 91 Mhz, so bandwith will fit a 100 mhz device.
Assuming everything synchronous, and ram has no problems with mixed read/writes (SRAM) then use a mux that switches all address/data/rw lines.
It has to give out of 5 timeslots 4 to the...
Same way as you would do it in C (or whatever language you use):
- use a counter to address the whole array one by one:
at seach start set register to max value, and coutner to 0.
for every data read:
- compare output with a register
- if lower, load register with read value
Hope this helps.
Is the PHY already creating a datastream and a clock for you?
If yes, then life is simple:
Just shift the data into a 8 bit shift register, and compare the parralell outputs to be equal to 00011101 pattern. Then reset you bit/byte counters with that signal.
Hope this helps.
How much support of isa do you need:
-8/16 bit transfers?
-IO addressing ?
-Memory addressing?
-DMA?
-correct ISA access timing?
If you like all, it is a more complex task.
Have not looked at the CPU you mentioning, but likely only supporting for only 8bit mem addressing, likely you don't...
Re: Metastability?
Metastability is unavoidable if you have multiple async clock domains.
Ways to transfer information between clock domains are:
- multiple flip flops inseries - one signal one direction, slow, simple
- Fifo - wider databusses & higher datarates possible, complex
- smart...
Re: vhdl help
Creating a pulse less that one clock cycle, is notmally never needed. Also it is not a good design appriach for a fully sunchonoes design.
Normally you can always design, that a full clock pulse can be used.
Making smaller pulses, you must and the outptu of a flipflop with the...
I strongly suggest to use only vhdl or verilog, no grapical entry.
The graphics can not easily ported over to other compilers.
Sadly making top level design on larger fpga is a very long task, but for that there are some scripts available to help you out.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
