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Hi linuxluo,
Yes, metal fill is req but what i mean to say is if you do standard cell / custom cell u no need to do that ,because top level guy who uses ur cells in his full chip/module level will clear these voilations at that stage. If you want to do metalfill for standard...
layout picture +asic
Hi,
Are you doing physical design for full chip/module or doing custom layout (like standard cells etc..,) .
If you are doing lcustom design no need to bother about metal fill, if you do metal fill in custom layout it will uncessarly consumes the routing grids...
Re: Technology related query
Yes, incase of flash memories we have to gates for a transistor one floating then 1 may be poly1 and poly2 respectively.
Thanks,
Rajesh
what is pdk
Hi,
PDK is the library information which contains .libs , and schematic,layout data files...., We require this if u use virtuoso layout editor (CADENCE) of mainly custom design tools.
--Arimilli Rajesh.
Added after 2 hours 17 minutes:
It contains Capacitive and resistive...
spice example and 90nm
Hi,
EDA tools generally manipulate using the data from .lib which delays are from spice simulations.
Lets say in your libary u calculated the delays for 100ff and 300ff ,if the tool see the load of the cell is 200ff ,it manipulates using some alogorithms using...
Re: Technology related query
Hi ,
poly1 and poly2 may be used in multi(High,low) vt cells, may to differenciate the high vt and low vt (certainly the sio2 layer thickness is different in both) it may be poly1 and poly2.
Thanks,
Rajesh
Re: Hard macros
Hi ,
Hard Macro's are usually custom cells / IP which we get from other IP vendors, It is an abstracted view of the IP/Custom cell ,we no need to do design closure with in this hard macro. We just use them like any other standard cell.
-Arimilli Rajesh
Hi ,
For SOC encounter .v (syn netlist) is not only the input file.We have to give the LEF file which contains the abstract view of the cells used in the netlist file.
We cannot see cells in mask level , we can see in abstract level, i.e input and output pins and routing blockages and...
for 45nm what do be the interconnect delay
Hi,
Basic gate delay will be of an invertor you can open the .lib and check the delay values for invertor.
But you will get only were approx delay.
If you know your decoder circuit pin functionality, you can find the exact delays by using...
Hi Prasad,
Check your tech LEF file , it should contain the IO cell information,if it doesnt have that information, contact your library team, because we have to design IO cell and layout it using virtuso(icfb) .
If that was not ready with your library team :
--Ask what are...
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