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Recent content by aravi.ab

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    dpram without inferring a memory block from fpga

    hi all, I am new to fpga and vhdl. I am trying to design dpram without inferring a block memory.But if I use 2d array in vhdl,While synthesizing the code it automatically inferred the block ram.I want to do it with only registers. thanks
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    [SOLVED] RAM modeling in VHDL using buffer types

    Hi, Can we use buffer types instead of array types to model memory and a tri sate buffer to enable and disable the read and write pointers in VHDL. for eg : TYPE mem ARRAY IS (0 to 32) OF STD_LOGIC_VECTOR(7 downto 0) or can we write like this TYPE mem BUFFER IS (0 to 32) OF...
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    FIFO read & write pointer synchronising for asynchronous FIFO

    HI, I have a doubt regarding read and write pointer. If the read pointer is synchronized with write pointer for comparison and read pointer is continuously incrementing in its clk domain.doesn't this pose a problem during comparison. thanks Aravind
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