[SOLVED] RAM modeling in VHDL using buffer types

[aravi.ab]

Hi,

Can we use buffer types instead of array types to model memory and a tri sate buffer to enable and disable the read and write pointers in VHDL.

for eg : TYPE mem ARRAY IS (0 to 32) OF STD_LOGIC_VECTOR(7 downto 0)
or can we write like this

TYPE mem BUFFER IS (0 to 32) OF STD_LOGIC_VECTOR(7 downto 0)

 

[FvM]

Re: RAM modeling in VHDL

Buffer is just a variant of the output type that can be read-back internally. The interface of a RAM model will necessarily use an inout type for the data port. Building a RAM model involves multplexing a memory array to the data port for read and write.

I guess, you should start with learning VHDL syntax. Both examples in your post show incorrect syntax. Or study existing RAM models from a text book or a vendor tool tutorial.