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Recent content by aramis

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    Synthesising design with memory macros

    I used to have the question about the memory macro. There is no need to synthesis the memory macro, just put the lib/db file into your design compiler library path and link with it. please see **broken link removed**
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    Read vendor technology files into synopsys DC_shell ?

    synopsys technology files hi, i can sure it's license problem..... check out for a valid licens...
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    Help me learn use nc-verilog in command line mode

    ncvlog uselib error It's strange, may i ask you a question?? which version of ncverilog do you use?? and i think `uselib is the syntax of verilog-XL instead of verilog so check out your document of ncverilog to find out this. besides, instead of using 'uselib syntax i always use "-y path of...
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    SystemC , Systemverilog , vera , specman...

    If i'm wrong, please correct me. I think systemC will not be as important as before, cuase synopsys will start to push their systemverilog, Cadence used to not support systemC in their flow. but when systemverilog is out, cadence start to push SystemC with their verification library. In many...
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    How to decrease time slacks in Synplify Pro?

    Re: Synplify Pro timing the same situation with me, i don't know what happen or what new constraint i should need....
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    2 NIOS processors instead of RTOS

    I never used such method, but i think it depends. The use of RTOS is more flexible, if you want to add new feature to your project. But if your project only has specfic function and will never add new function, it is enough without using any RTOS, just forgot RTOS. Just Compare RTOS sw...
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    Library Compiler User's Guide

    I guess it is syn@psys library compiler, it shouldn't post here.. this guide is available in SOLD. aramis
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    News::: Verplex will be acquired by Cadence !

    The information shows more and more people use formality( idon't remember where to find the report), maybe just because they use syn@psys synthesis and backend tool and formality integrate well with syn@psys flow. of course, verplex is still no. 1. cadence recenlty focus on their unify...
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    News::: Verplex will be acquired by Cadence !

    Re: verification Verplex is indeed the leader of "formal verification" technology, before synosys FormalPro . i think few people know them because formal verification is not widely used by designers. aramis
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    Looking for any Verilog Indent tool

    verilog indenter Is there any Indent tool for verilog, like C -indent?? thanks aramis
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    question regarding Synopsys VERA

    Re: Vera You need VERA to compile vera code, then link it with any simulator to run simulation! as i know, VCS 6.1 or after can support vera! but i do vera with cadence verilog. the main conern to develope VERA on winNT is not simulator, because VERA compiler only support UNIX/LINUX...
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    Req: seamless documentation

    manuals here is the manual
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    Req: seamless documentation

    I have got this document nearly, if anyone need it, PM me i'll upload it here
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    Where can I find Specman-Elite materials???

    Hi, if your tutorial ppt is not avaiable from installed directory, can you upload it here, i think many people will be thankful!! besides, Specman is a powerful tool, and do you ever try VERA?? i hear somebody tell me that VERA is more easy to learn. aramis
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    Dual CPU PC and LINUX for EDA!

    linux kernel after 2.4 support dual CPU, so you just install the latset version from Redhat, Mandrake will be fine. but i am not sure which EDA tool for linux can utilize these features, maybe should try it

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