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Recent content by AOQ

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    Reference voltage generator for Pipelined ADC

    Dear all : as the attachment shown, the reference voltage generator ( for Pipelined ADC testing PC Board) is implemented by two resistors, two capacitors, and two unit gain buffer. My questions are as follows: 1. What's the purpose to add two 10Kohm resistors in series in the positive...
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    Question about SAR ADC using attenuating cap

    Dear all : I am designing SAR ADC using attenuating capacitor, should the top plate of subDAC be discharged first ? thx.
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    Reference voltage for SAR ADC and comparator resolution

    site:www.edaboard.com aoq thx for answering. so the resolution of comparator is related to the operation speed ? Thx.
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    Question about split cap array ( for SAR ADC)

    Dear all : In my technology, about 50fF unit cap can achieve 10 bit resolution for CDAC type SAR ADC. Now if I use split cap to reduce total capacitance, the result is bad. Does anyone know what the effect for using split cap array ? How large unit cap shoud I use ? thx~~
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    auto zero of latch comparator?

    comparator autozero Maybe u need add preamps with capacitor couple so than u can do input or output or multi-stage offset cancellation the residue offset is mainly determined by the gain of preamp see razavi's book for detail Best Regards :D
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    HSPICE or SPECTRE for simulation of a complete AMS chip

    Re: HSPICE or SPECTRE I think spectre is more convenient for mixed-signal simulation. Best Regards:D
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    Reference voltage for SAR ADC and comparator resolution

    offset-voltage gain adc preamp comparator Dear all : I am designing a 10b single-ended, charge redistribution type SAR ADC in 0.35um CMOS. Supply voltage is 3V and power budget is 100uW. Conversion rate is 10~100KSPS. I hope to achieve rail - rail input range, thus I need a voltage near...
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