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Recent content by anovickis

  1. A

    Implementation of an algorithm in FPGA

    you are on the correct path, but I would suggest building models for each section and then verify your vhdl code along the way with some modeling environment. For coefficient picking you can always model in C or modelsim - I would not use vhdl as the area to pick coeffs. Code that only after...
  2. A

    How to write set of instructions in ROM of 8088??

    8088ROM also, get yourself a copy of something like link&locate tools for the linking step.
  3. A

    How you know what is CDC

    cdc occurs when you have a signal that crosses from one clock domain to another clock domain
  4. A

    Basic Verilog syntax question

    Verilog COde Problem as far as the original question - neither is clocked process so the generated logic is equivalent.
  5. A

    are there any visual C++ to VHDL converter out there?

    conversor de c em vhdl the easiest method get catapult is to bring a somewhat large bag of gold to to someone at mentor.com see h**p://www.mentor.com/company/news/catapult_sl.cfm
  6. A

    Erroneous "combinational loops" warnings

    synplify rename my signals Yes we should use clocked, but .. still it should work as it is - I'm thinking this appears to be bug. The logic actually generated looks correct though Leo spec does not complain about this and the schematic is correct. Have you tried submitting to SOS ? I'm...
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    General Tips of reading Verilog Code

    wangkl - well put , that is very similiar to my adopted strategy each of those items requires a _seperate_ and _distinct_ study before the exact function can be understood. I will add that with many designs the documentation is non-existant poor or incorrect - so be careful if you start with...
  8. A

    How is job opportunities in San Jose, USA

    san jose / silicon valley varies quite a bit on salary - but instead of me giving you numbers I suggest also to be careful when you look at the numbers you see that you take into account that it is an expensive area to live in. If you make less than 100-120k/year there you are likely not going...
  9. A

    Erroneous "combinational loops" warnings

    combinational loops In general you need to add clocked logic to get rid of those sort of things. :|
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