Basic Verilog syntax question

[choonlle]

Verilog COde Problem

what is different between


wire a;
reg b;
a) always (*)
a=b;



b) assign a=b;


????

 

[echo47]

Verilog COde Problem

Please show a complete working example, so we can better understand what you are trying to do.

always (*) is a syntax error.

Your first a=b is an illegal reference because the left side of a blocking assignment must be a register.

 

[nand_gates]

Re: Verilog COde Problem

always(*) is not an error accoding to verilog 2001 std.
assgn a=b; will take more simulation time than
always(*) a=b; where a has to be of type reg as pointed out by Echo!
For more information please refer to ncsim simulation guide.

 

[echo47]

Verilog COde Problem

I know about always @ (*), but what is always (*)?
I couldn't find it in the standard, and my simulator and synthesizer both reject it.

 

[nand_gates]

Re: Verilog COde Problem

Yes you are right!
always@(*) is the correct syntax!

 

[anovickis]

Verilog COde Problem

as far as the original question - neither is clocked process so the generated logic is equivalent.

 

[bangash]

Re: Verilog COde Problem

When the number of input variables to a combination logic block are very large, sensitivity lists can become very cumbersome to write. Moreover, if an input variable is missed from the sensitivity list, the block will not behave like a combinational logic block. To solve this problem, Verilog HDL contains two special symbols: @* and @(*). Both symbols exhibit identical behavior. These special symbols are sensitive to a change on any signal that may be read by the statement group that follows this symbol.[1] Example 7-17 shows an example of this special symbol for combinational logic sensitivity lists.

[1] See IEEE Standard Verilog Hardware Description Language document for details and restrictions on the @* and @(*) symbols.

Example 7-17 Use of @* Operator
//Combination logic block using the or operator
//Cumbersome to write and it is easy to miss one input to the block
always @(a or b or c or d or e or f or g or h or p or m)

begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m;
end

//Instead of the above method, use @(*) symbol
//Alternately, the @* symbol can be used
//All input variables are automatically included in the
//sensitivity list.
always @(*)
begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m;
end

 

[janarthanan]

Re: Verilog COde Problem

the main difference between the two statements(assuming no syntax error):

both will evaluate the LHS expression, but

in case of
a) the expression within the always will be evaluated with respect to sensitivity list.
b) the expression is evaluated whenever the RHS changes.

 

[darylz]

Verilog COde Problem

the same

 

[suman_vinnu]

Re: Verilog COde Problem

one is procedural statement and other is continuous assignments.

Added after 2 minutes:



moreover for always a should be reg when u assign some value it as to store so it may give u error ,this error will not occur in 2 statement

 

[indomitable12345]

Re: Verilog COde Problem

in the first one,the operand on the left side has to be a reg...however as far as synthesis is concerned,both if them will synthesize the same logic...