lambtron
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found combinational loop during mapping
Anyone know how to eliminate false "Warning: found x combinational loops!" messages from Synplify? Specifically, the problem is that this warning pops up wherever I have a bidirectional bus interface. I am using Lattice Semiconductor's ispLEVER Starter Synplify 5.0.01.73.31.05.
For example:
Synplify generates the following warnings for the above code:
Any ideas would be appreciated!
Anyone know how to eliminate false "Warning: found x combinational loops!" messages from Synplify? Specifically, the problem is that this warning pops up wherever I have a bidirectional bus interface. I am using Lattice Semiconductor's ispLEVER Starter Synplify 5.0.01.73.31.05.
For example:
Code:
-- junk.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cpld is
port (
dir: in STD_LOGIC;
a_bus: inout STD_LOGIC;
b_bus: inout STD_LOGIC
);
end cpld;
architecture Structure of cpld is
signal i_a_in: STD_LOGIC;
signal i_a_out: STD_LOGIC;
signal i_b_in: STD_LOGIC;
signal i_b_out: STD_LOGIC;
component G_BIDIR Port (
I : in std_logic;
OE : in std_logic;
O : inout std_logic;
FBK : out std_logic );
end component;
begin
A_BUS: G_BIDIR port map( I => i_a_out, OE => dir , O => a_bus, FBK => i_a_in );
B_BUS: G_BIDIR port map( I => i_b_out, OE => not dir, O => b_bus, FBK => i_b_in );
i_a_out <= i_b_in;
i_b_out <= i_a_in;
end Structure;
---------------------------
library ieee;
use ieee.std_logic_1164.all;
entity G_BIDIR is Port (
I : in std_logic;
OE : in std_logic;
O : inout std_logic;
FBK : out std_logic );
end G_BIDIR;
architecture behavioral of G_BIDIR is
begin
O <= I when OE='1' else 'Z';
FBK <= O;
end behavioral;
Synplify generates the following warnings for the above code:
Code:
Warning: Found 1 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN134 :"junk.vhd":57:4:57:5|Found combinational loop during mapping
1) instance A_BUS.O_1 work.cpld(structure)-A_BUS.O_1, output net "a_bus" in work.cpld(structure)
input nets to instance:
net "b_bus" in work.cpld(structure)
net "dir" in work.cpld(structure)
End of loops
Warning: Found 1 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN134 :"junk.vhd":57:4:57:5|Found combinational loop during mapping
1) instance A_BUS.O_1 work.cpld(structure)-A_BUS.O_1, output net "a_bus" in work.cpld(structure)
input nets to instance:
net "b_bus" in work.cpld(structure)
net "dir" in work.cpld(structure)
End of loops
Any ideas would be appreciated!