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Recent content by anjankumarkn

  1. A

    How to calculate uo * Cox for 50nm Technology

    Hi, How do we find µn * Cox for nmos transistor by hand calculation and by operating point analysis in Cadence(Print DC operating points)? With Diode connected mosfet and drain connected to a current source, I get µn * Cox = 223u With gate and drain connected to a voltage source, I get µn *...
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    Why we often change W in current mirror not L

    Hi, While designing a current mirror, many times we play around with "W" but not "L". eg: if I need a current of 2I, then I increase W --> 2W, and not L--> L/2. One reason may be due to channel length modulation. Is there any other reason in doing so? Thanks!
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    [Moved]: Biasing the MOSFET using a Drain to Gate feedback resistor

    How high resistance between Drain and Gate can have better gain? Please shed some light on it.
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    [Moved]: Biasing the MOSFET using a Drain to Gate feedback resistor

    Hi, For biasing a MOSFET with Drain and Gate connected through a resistor need a big resistor. Why we need to use big resistor? Will shorting Gate and Drain work for Biasing (still the current in feedback path is 0)? Thanks!
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    Temperature effects on threshold voltage and mobility

    Thank you!
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    Temperature effects on threshold voltage and mobility

    Hi, It is learned that threshold voltage and mobility decrease with increase in temperature. How can we intuitively justify the statement? Thanks, Anjan
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    How to maintain ID constant by increasing VGS

    Thank you very much!
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    How to maintain ID constant by increasing VGS

    What I have learnt so far is ID(Drain current) is a function of VGS(when the MOSFET is operating in active region). Is there any way to maintain ID constant by increasing VGS? Thanks
  9. A

    Cadence differential pair layout

    For Diff Pairs we prefer cross coupled matching. AB BA
  10. A

    scope of VLSI and analog design in next 5 years.....

    Ajay, Thank you very much..... Do you have any idea about the companies doing analog design work in India?????? If possible send me your email id????? Thank you
  11. A

    scope of VLSI and analog design in next 5 years.....

    Hi friends, Can i know the scope of VLSI and analog design in next 5 years????? Also can i go to USA with 2 years of experince behind me in VLSI field???? And for post graduate program VLSI is a good choice or not(masters in US)?????
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