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Recent content by andrea22

  1. A

    help with cmos tg dynamic shift register

    If both transmission gates (billteral switches) can be closed at the same time that will causing mixing of old and new data and therefore loss of data integrity! Is that right?
  2. A

    help with cmos tg dynamic shift register

    That is happening when I use overlapping clocks, really I get smaller voltage then Vdd (Vdd=5v,and I get 2.5v). When I used non-overlapping clocks everything is ok.
  3. A

    help with cmos tg dynamic shift register

    As you see this shift register is consists of 4 dynamic d latches or two d dynamic flip-flops. With non-overlapping clocks shift register works ok. But when I use overlapping clocks at the output of the second inverter I get smaller voltage then Vdd (Vdd=5v,and I get 2.5v),that's what I don't...
  4. A

    help with cmos tg dynamic shift register

    Does anyone have any tutorial about cmos tg dynamic shift register? I need an explaination how this circuit works. What I ment why this circuit only works with non-overlapping clocks, or why this circuit can't work with overlapping clocks? I need to prove why this circuit can't work with...
  5. A

    dynamic shift register

    These are my diagrams.The third diagrams is at the output of pass transistor. What is happening when Phi1=0,Vin=Vdd and Phi1=0 and Vin=0?
  6. A

    dynamic shift register

    Do you have any literature about pass transistors? Why when I simulated this circuit,when voltage on gate of pass transistor is zero (0 V),I get that voltage at the output of pass transistor is negative (small negative voltage)? What I ment when Phi1=0 or Phi2=0? When Phi1=Vdd and Vin=Vdd...
  7. A

    dynamic shift register

    Hi, Does anyone know why are need non-overlapping clocks in dynamic shift register? Or why this circuit doesn't work with overlapped clocks? Can anyone draw timing diagrams in point A0,A1,A2,A3?
  8. A

    Generate two non-overlapping clocks

    Ok,thank you very much.
  9. A

    Nonoverlapping clock generation

    Thank you very much.:)
  10. A

    Nonoverlapping clock generation

    So,in feedback loop,delay element (inverters) must be even number, two,four,six....inverters must be used as delay elements,is that right? ---------- Post added at 15:47 ---------- Previous post was at 15:45 ---------- Why is that?
  11. A

    Nonoverlapping clock generation

    Yes,I ment that that can't work (with NAND gates) The first circuit you posted works only with third inverter which is output of the feedback loop.(first picture I posted) The second circuit works only with two inverters in feedback loop.(NOR gates).When I add third inverter it can't work. I'm...
  12. A

    Nonoverlapping clock generation

    No,it can't with two inverters if you use NAND gates. I tried that in PSpice. With NOR gates only two inverters can generate non-overlapping clocks,with three it doesn't work.
  13. A

    Nonoverlapping clock generation

    Ok,but why needed trhee invertrers to generate non-overlapping clocks? Why when we realise non-overlapping cloks with NOR gates only two inverters are neeed?
  14. A

    Generate two non-overlapping clocks

    I know the diffrence between NAND and NOR if you mean on logic table. But dont understand why are three inverters needed? Can you explain me how this circuits works,please? What I ment is how each logic gate in this circuits effects on non-overlapping time? Because when I simulated this circuit...
  15. A

    Generate two non-overlapping clocks

    I simulated those two circuits in PSpice.Why this feedback loop needed? Does NAND gate and NOR gate have diffrent delay so why is diffrence in number of inverters? Well,I need more explanation,I'm really confused.
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