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dynamic shift register

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andrea22

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Hi,
Does anyone know why are need non-overlapping clocks in dynamic shift register?
Or why this circuit doesn't work with overlapped clocks?
Can anyone draw timing diagrams in point A0,A1,A2,A3?
 

When the clocks overlap, all the pass transistors turns on at the same time, and the whole logic becomes a combinatorial buffer. No longer a shift register.
 

Do you have any literature about pass transistors?
Why when I simulated this circuit,when voltage on gate of pass
transistor is zero (0 V),I get that voltage at the output of pass transistor is
negative (small negative voltage)?
What I ment when Phi1=0 or Phi2=0?

When Phi1=Vdd and Vin=Vdd maximum voltage at the output of pass transistor is Vdd-Vtn?
How this effects on CMOS inverter?(inverters are realised in CMOS technology)
 
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When Phi1=Vdd and Vin=Vdd maximum voltage at the output of pass transistor is Vdd-Vtn?
yes
How this effects on CMOS inverter?(inverters are realised in CMOS technology)
You have to design the inverter to make it work with the threshold accordingly.
 

These are my diagrams.The third diagrams is at the output of pass transistor.
What is happening when Phi1=0,Vin=Vdd and Phi1=0 and Vin=0?
 

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