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Recent content by anandkris84

  1. A

    UART and SPI relation

    I am working with 8051 and I wanted to know how are UART and SPI related as in: 1.Can they not be present individually. 2.Is it that during transmission-the UART provides data to SPI --if that is the case does the serial buffer of UART provide data to trnsmit buffer of SPI.
  2. A

    Problem in implementing differential logic Cadence Encounter

    While trying to create differential pair of signals using Route flip chip signal ,I fill the advanced options form and in that I select "Named" nets under that.But when I enter the nae of the name of the nets,it says cannot find "those particular" nets in design.then **No net has been...
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    Place and route options in Cadence Encounter

    I would be thankful for the replies..I am sure a lot of u guys wud know about it.
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    Urgent:Calculating wire capacitance

    I need to find the wiring capacitance of a path in a circuit made using CMOS,I wanted to know how do the wiring capacitance at the gate of the CMOS and the drain of the CMOS add..Please help,I have a project submission pretty soon
  5. A

    Failed to find DRC rules divaDRC.rul

    I am trying to get the DRC check in Cadence Virtuoso for a design synthesised using Synopsys Design Compiler but I am constatntly getting the error Failed to find DRC rules divaDRC.rul. I have checked the path and the file is present there.But I fail to understand why I am getting this error
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    Place and route options in Cadence Encounter

    I am working on analysing the effect of various place and route schemes on the capacitance of a circuit. So,please let me know the different place and route schemes used in Cadence Encounter in the order of optimality it provides
  7. A

    How to generate a physical layout of a synthesised VHDL file

    Re: How to generate a physical layout of a synthesised VHDL Yeah I used a place and route tool(Cadence Encounter) and then got the layout in virtuoso
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    Use VHDL file in Cadence Encounter

    I have a synthesised VHDL file using Synopsys Design Compiler.Can I get the physical layout using Cadence encounter and how? as to me it seems that the input file for Cadence Encounter is a Verilog file.
  9. A

    How to generate a physical layout of a synthesised VHDL file

    I have a synthesised vhdl file with TSMC 180 nm library using Synopsys Design Vision. Now,I want to have the schematic using Cadence Virtuoso.How to do that ?
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    Urgent:ui-59 error in Synopsys Design Vision

    I am trying to get a physical layout of the vhd file using Synopsys Design Vision. But in the read operation from the GUI,I am constantly getting an error that the particular file.vhd is not present in the default work directory. I actually have the file.vhd in the work directory and also the...
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