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Recent content by amsut

  1. A

    From gate-level to transistor level

    Can anyone help me ? Which tool in SYNOPSYS is capable of converting the gate-level design to the transistor-level design ?
  2. A

    SPEF annotate with multiple submodules design

    write_parasitics -format spef Excuse me, can anyone help me ? The problem is i have designed a quite large design contains 4 generation : grand_father, father,son and grand_son. After design i have annotated the parasitics elements and RC trees through the : write_parasitics command directly...
  3. A

    Need Verilog code for sine wave

    vhdl code to generate sinwave Oh ! So it was fine,my friend. Misunderstood in the begining makes us becomes closer friend in future. But seriously i can not enjoy the word "steal" you used :D .... Have a nice day man . Added after 15 minutes: Master Echo47, if i do not mistake ModelSim...
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    Need Verilog code for sine wave

    sine lockup table Steal ? I laugh at that, this simple stuff can be invented by anyone even the elementary level student who just have some basic idea of HDL and DSP. The VHDL code in the site you refer to is also based on sampling and quantizing which are DSP concept only ... Yes in...
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    Need Verilog code for sine wave

    verilog $sin But this function is not synthesizable ... I know 1 lame trick to generate the sine wave from DSP concept but really i havent never got enough courage to convert this trick to HDL , it was too long .
  6. A

    swtiching activity from a Vcd file

    dump .vcd parsing vcd2saif work in VCS or VCS-MX ..... 2nd option you can reannotate ur switching activity file by changing the system task in your testbench file ....
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    Blogspot for ASIC verification

    It looks too too simple and very less topic. But anyway all the best for you and ur plan ...
  8. A

    Passing parameter to Design Compiler

    I have writen a Verilog code for my design, in some sub module i have parameterized them. Now i'm facing a problem that when i retranslate my behavioral level design to a gate-level design, all my parameter becomes fixed at the default values and cant be change. Is there any way to resolve this...
  9. A

    Need advice regarding NanoSim

    Hi everybody, i'm the new commer in AMS field. I have faced the difficulties in using NanoSim for nearly a week, can anybody help me to solve it ? My problem is, i have design some standar cell ( like nand,nor and,or, Dlatch ..etc ) and i wish to analyze their timming violation as well as...
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