Passing parameter to Design Compiler

[amsut]

I have writen a Verilog code for my design, in some sub module i have parameterized them. Now i'm facing a problem that when i retranslate my behavioral level design to a gate-level design, all my parameter becomes fixed at the default values and cant be change. Is there any way to resolve this problem without rewriting each every seperated codes for each value of parameter ? Thanks in advanced ....

 

[atena]

Try this : elaborate [module_name] -library WORK -param #[parameters_value maping]# -update

Surely your problem will be resolve, but it will be a quite boring and massive stuff .

 

[XHL]

You can not use parameters in your gate level netlist - maybe you can set these prameters as input of your blocks or make them be configured by your i2c/spi protocol.

Another easy method is to put all the parameters in one block whose output connect to all other blocks that use the parameters. This way you can include this file for both rtl/gate simulation.