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Re: can Switch Capacitor CMFB, redue the over all gain of a
yes sc cmfb circuit can reduce the gain by loading the output. Your switching capacior you can consider as switch resistor (1/C*f) which can reduce the gain.
while choosing the value of the capacitor for the sc cmgb ckt you need to take follosing care.
1) Capacitor is size is big enough so that the droop in output common mode is withing range.
2) Capacitor size should be below the value where it start loading the circuit and reduce the gain (sc...
Re: a problem of LDO
is 40degree is the phase margin of the full LDO or opamp alone.
what is the min and mnax current variation.
If 40degree is the phase margin of the entire system then under what load(current)
you have simulated this and what is the phase margin in another case.
Is it...
railbased esd
Hello doctor,
Can you expalin bit more about the pad clamp. Why we need clamp only for the pmos transistor sitting on the pad and not for the nmos. Why they say that then nmos is more robust for ESD zap. Is ggnmos is clamp.
What is the rule of thumb for placing the clamp and rail...
Re: how can I get a transferfunction about a loop filter in
There is one good thesis by Mozhgan Mansuri wher you can find good material on loop dynamics. I am attaching same here
Re: sc-cmfb problem
have you check the gain reducton of the amplifier with loading effect of the sc cmfb. Higher the cap lower will be the resistance and lower will be the gain of opamp.
What clk freqecy you are using for sc cmfb.
When the pfd update frequency is comparable to loop bandwidth. the continious time modelling of PFD does not hold good. And then you have to take the DISCRET (I mean sampling effect) of the PFD.
Sampling effect manifest in term of folding of the out of band noise into the pll bandwidht and hence...
Re: Delay buffer in Ring VCO
hi i think that cross couple pair are provided to get teh positive feedback...which will reduce the rise and fall time of the wavform and hence reduce the rms value of ISF which in turn reduce the flicker noise upconcersion...and hence teh close in phase noise will...
A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture
Zhinian Shu Ka Lok Lee Leung, B.H.
This paper appears in: Solid-State Circuits, IEEE Journal of March 2004
Can any one forward me this paper.
Amit
ntat cmos
well i am not sure...but it has to do some thing with the curvature of the output voltage waveform with respect Temperature...
so what is feel that order has to do soem thing with the curvature correction of the output voltage.
since the output voltage of the bandgap has certain...
from icfb window create new cellview change the view to either verilog-a or verilog-editor what ever you are want....one window will popup...write your verilog-a or verilog code into it along with all your inputs and output..
save and close the window. if your entry is correct symbol editor...
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