Rail Based ESD protection technique for integrated circuit

[alok_ky]

esd pad protection

What rail based ESD ?
How is it different from Pad based ESD ?

Any references (documents etc) ?

 

[DoctorProf]

eos & esd difference

Rail based ESD protection puts steering elements (usually diodes) on the inputs to and ESD Positive rail and an ESD Negative rail. These elements steer the charge to these rails. The rails are ususally VDD and GND but do not have to be. I have used floating rails dedicated to ESD also. Betwen these two rails you would place a set of clamps to limit the voltage developed between them. Car must be exercised to keep the series resistance low between the steering diodes and clamps otherwise excessive voltage drop can devleop causing ESD problems. You may have to put more clamps between the rails and distribute them around the chip to reduce this voltage drop. Since the steering element operates in forward conduction mode its ESD capability is very good and its size can be small. The Rail clamps are shared between pins so even if they are large there is only a few per die.

Pad based proteection places the clamp locally at the pad. Because of this the clamp can occupy much of the pad cell. It porvides better local protection but needs to still have a good current return path (usually ground). If you have a P juntion to the supply tied to the pad you will also need to proivde an alternative path or this junction might get damage. The so called "Fail Safe" design does not have a junction to the positive pad and can safely use pad based protection.

The ESD Association (www.esda.org) sponsers the EOS/ESD Symposium. The tutorials from this Symposium are very helpful to understand the difference between Rail and Pad based protection. You will find papers from Texas Instruments are mainly pad based snap-back based protection. Papers from Freescale(Motorola) are rail based protection. There is a symposium coming up in September. It will be held in CA athis year.

Dr.Prof

 

[amitbhaiji]

railbased esd

Hello doctor,
Can you expalin bit more about the pad clamp. Why we need clamp only for the pmos transistor sitting on the pad and not for the nmos. Why they say that then nmos is more robust for ESD zap. Is ggnmos is clamp.
What is the rule of thumb for placing the clamp and rail to rail ESD.
Thanks.

 

[DoctorProf]

why we need fail-safe pads

Pad based protection places a clamp (grounded gate NMOS, ggNMOS) between the pad and ground. This is a snap-back device. Most of the current foundries (TSMC, etc.) use a silicide block layer in these NMOS devices and they could use other techniques to insure uniform turn-on of all fingers. These techniques are gate coupling, zener triggering, resistor to ground on the gate. All of these attempt to place a small gate voltage on the NMOS to help get more uniform turn-on of the bipolar.

I believe you are a little confused about the PMOS. If there is only NMOS junction connected to the pad (i.e. No path to VDD) then you only need this single NMOS to ground. The problem is that many pins have both NMOS and PMOS connected to it. In this case you have to provide an ESD path from the pad to VDD that does not go through the sensitive circuit. A forward biased diode (anode on pad, cathode on VDD) provides this path.

The foundry ground rules typically has the minmum needed size necessary to provide some specified level of ESD protection (typically 2000 HBM). I would design conservatively here making the devices bigger than they specify because I have not had good success with their minimum designs rules.

Dr.Prof

 

[magneticflux26]

Re: why we need fail-safe pads

Hi Dr. Prof,

I was reading the thread and noticed that you mentioned this:
"The rails are ususally VDD and GND but do not have to be. I have used floating rails dedicated to ESD also."
I'm implementing the same idea in my thesis, but my professor is asking how will the inverter circuit or RC circuit
on the power clamp can be biased if there is no Vdd rail is floating.

I will highly appreciate your reply
Thank you.

 

[dick_freebird]

I dislike rail (2-ring) ESD schemes because you cannot avoid having
the ESD clamped voltage appear across the entire core of the chip,
and those are the weakest, most aggressively packed and most
leisurely tied-off devices (ESD rules enforce stiffer guardrings, not
point "taps", and more spacing).

My preference is for pad ESD in a star-ground arrangement. Only
the supply pin path(s) then impact(s) the core. And there is no
potential for input signals to pump the supply when depowered.

But then you need a breakdown type clamp (or active) per pad.
If you don't have circuit-under-pad allowed, or fat bussing going
to waste nearby, this will cost you.