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If IO cell is placed in IP, but BUMP cells are added later by the IP consumer. Thus, IP consumer get an HARD MACRO with 'class bump' attribute on some pins.
I mean that in the version of LEF 5.7 or greater, port CLASS attribute can be set equal to {CORE | BUMP}.
From "LEF/DEF Language Reference": "BUMP—Specifies the port is a bump connection point. A bump port should only be connected by routing to a bump (normally a MACRO CLASS COVER BUMP cell)"...
Hi all,
I'm implementing IP using Flip-Chip floorplan, so several IO ports must be connected to bumps.
How to set attribute CLASS BUMP in LEF file for several IO ports when writing out LEF (not by hand)?
Now this attribute is "CORE" by default. Tool - cadence Innovus 17.1.
Hello,
i have a project in Cadence Encounter with hierarchical blocks, where full-chip IR-drop analysis is needed.
For each hierarchical block i have .LEF, .DEF files and current files (.ptiavg).
I generated the hierarchical PGV (HPGV) for each block in the design.
Design has a feature - global...
Hello,
i need to use cadence RC compiler for boundary scan insertion with separate TAP-controller in verilog module. Design does not contain any PAD logic (this is part of SoC).
Can anybody tell me, it is possible to automatically insert boundary scan logic without PADs instantiation?
I made a Place&Route in Encounter and got netlist+SDF for simulation.
Possibly, for simulation of design with gated and multiplexed clocks needs an Clock Tree building, i.e. post-map simulation is not required..
I think, solution is place&route or verilog/sdf modification (as mentioned by...
Hi all!
I have design with clock multiplexers and clock gating cells. I'm using Cadence RC compiler for synthesis. After synthesis, i need to simulate resulting netlist with SDF file using ncsim.
When i run the simulation, i see that clock MUX and gating cell delays are not '0'. How to get an...
Hi all,
I'm working to implement USB2.0 device on Spartan-6 LX150T development kit. I use on-board PHY (NXP ISP1504A1) with ULPI interface.
I also use a USB logic analyser (FS only).
In HS, device working stable and is always recognized on host. In full-speed work is unstable, device is often...
Thank you all for answers!
I have successfully synthesized a netlist. I have disable timing check in my 2-FF synchronizer module using cadence timing file (ncelab -tfile).
Simulation netlist completed successfully.
No, i'm don't use a data signal as a clock. spi_clk is interface signal (SPI_CLK).
Now i'm trying to use 2-FF synchroniser. First flip-flop transmits X to second flip-flop.
My synchroniser:
always@(posedge clk) begin
flop0 <= spi_clk;
flop1<= flop0;
end
I'm using ncSim. Is it a...
//synchronize async input (SPI_CLK) with system clock
always@(posedge clk)
spi_clk_r <=spi_clk;
//save the value to generate pulse
always@(posedge clk)
spi_clk_prev <= spi_clk_r;
//and detect rising edge of synchronized spi_clk (pulse).
//it used for data capturing
assign rising_spi_clk...
I want detect rising edge of SPI_SCK, but when SPI_CLK and system_clock edges occur simultaneously data corrupted.
The same thing happens with signal SPI_SS.
Hello.
I'm trying to synthesize the SPI slave in RC Compiler. After synthesis occurs race conditions between SPI_CLK and system clock (clk):
always @(posedge clk)
spi_clk_r <= spi_clk;
How to avoid the race conditions in this case?
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