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Recent content by alexpanrui

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    Mentor Graphics: AMPLE programming guide needed

    Hi, all, anyone has the AMPLE programming guide? I couldn't find any tutorial online. Thank you very much.
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    [Moved] 9-bit shift register Vs 3-bit counter. Which one has larger area?

    Great idea.
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    [Moved] 9-bit shift register Vs 3-bit counter. Which one has larger area?

    Hi, Klaus, Thank you for your replay. I am currently doing implementation with altera DE0-nano in Quartus II.
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    [Moved] 9-bit shift register Vs 3-bit counter. Which one has larger area?

    As mentioned in the title, which one has a larger area? What I am intended to do is to use shift register as a counter. E.g. If I want to count 8 times of certain operation, a 9-bit shift register is used to shift a binary '1' from index 0 to index 8. The operation stops when '1' reaches index...
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    vassert in testbench file

    Hi, all. I have a testbench file generated by perl. In it, it has this vassert, which is considered as unknown system task when compiled with icarus verilog. What kind of compiler do I need such that this vassert can be recognized? And where can I find documentation on this vassert? Thank you all.
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    [SOLVED] Help needed. Register a verilog model for an existing symbol in mentor graphics

    Hi, all, I am trying to register a verilog model for an existing symbol in mentor graphics. I followed the steps described in a training material by mapping pins and properties of the verilog model to an existing symbol. And then I performed the "check language views", but in the message area it...
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    How to insert pipeline registers in Design Compiler?

    Hi, all Is there any way to tell the DC to insert pipeline registers to the data path with huge combinational delay which leads to negative timing slack? Thank you.
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    Hold time violation on clock falling edge with no clock falling edge used in RTL code

    So what you mean is that as the timing of the asynchronous input is unknown versus the clock system, simulator will have to check the timing of this input against both the rising and falling edge of the clock. Am I right? And please bear with me, why is Mentor involved here? I used DC for...
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    Hold time violation on clock falling edge with no clock falling edge used in RTL code

    It is related to an asynchronous input.
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    Hold time violation on clock falling edge with no clock falling edge used in RTL code

    Hi, I was running post layout simulation in NCVerilog with lots of hold time violations on clock falling edge. The thing is that in my RTL design, i didn't use the clock falling edge to detect or trigger any signals. Can anyone explain to me why I am having the hold time violation on clock...
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