How to insert pipeline registers in Design Compiler?

[alexpanrui]

Hi, all
Is there any way to tell the DC to insert pipeline registers to the data path with huge combinational delay which leads to negative timing slack? Thank you.

 

[jbeniston]

Not exactly. You can add the registers after the combinational block in the RTL, and then enable register retiming to get it to balance it for you.

See the Design Compiler Register Retiming Reference Manual. It can make Formal Verification a bit harder though.