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Recent content by ajrox

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    ucos-II semaphore doubt

    In ucos-II semaphore can be used as an event notifying flag/signalling event. It's declaration is OSSemCreate(0) as per the book MicroC/OS-II: The Real Time Kernel by Jean J. Labrosse. How can a semaphore have an initial count of 0? Also can anyone provide an example code for semaphore as...
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    lpc 2148 4x4 keypad interfacing problem

    #include <LPC21xx.h> //#include <LCD.h> //#include <keypad.h> /*#ifndef KEYPAD_H_ #define KEYPAD_H_ #define KEY_PAD_PORT 0x000003FC void keypad_init(void); unsigned char detect_key(void); unsigned int getch_keypad_to_LCD(void); #endif /*KEYPAD_H_*/ */ const unsigned char...
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    publishing in journals for beginners

    thanx alqhtani & fredd one question do you have to be a speaker at these conferences or just submit your manuscript?
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    publishing in journals for beginners

    Hi, I am an under-graduate student(last year) in electronics & telecommunication. I wanted to know where can I publish my own paper/article (this would be my 2nd paper- I published my 1st in a relatively unknown journal). I know about IEEE potentials.But what are some other options?
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    Timing simulation in Xilinx

    Thanx TrickyDicky and std_match I got different results from timing simulation (post place and route) and behavioral simulation. What could have gone wrong ? ( i did use freq below that of max clock freq)
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    Timing simulation in Xilinx

    What is timing simulation?(Xilinx) Does it reasonably guarantee that the design will work in hardware? What are steps of Xilinx timing simulation?(should I write a test bench or force values in Isim or ModelSim)
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    bad synchronous description

    Thank you very much for helping!! and also thank you for taking time to rewrite the code
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    bad synchronous description

    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity...
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    complex code : signals or variables (vhdl)

    thanx std_match! also i wanted to ask-is it better to write modules for structural modelling or subprograms for behavioral modelling while designing a chip
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    what is the advantage of semaphore over use of global flag

    According to me if you are using a rtos and both the tasks are critical, use semaphore the rtos takes care of the rest. Global flag can serve the same purpose if only these two tasks are using it.However as ftsolutions says interrupts introduce many problems which cannot be predicted.
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    some questions on modbus

    I have some questions for modbus protocol.(rtu format) What are the start and stop bits for each byte that have to be appended?(modbus documentation does not mention this) Do all the bytes that have to be transmitted(namely-address byte,function byte,data bytes and crc bytes) have start,stop &...
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    complex code : signals or variables (vhdl)

    i'm writing a vhdl code for modbus protocol. crc calculations for a frame in modbus involve many arithmetic and logical operations. most of the calculations require immediate operations on the same object. i've used variables for this purpose and the simulation works to fine. however is it...
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    [SOLVED] CRC module :- bad synchronous description

    Thanx TrickyDicky!! it worked!
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    ieee membership for publishing

    i'm a beginner it's imp for me 1st to be recognized that's why i'm publishing later on if i progress good enough in the field i will certainly follow ur advice thanx - - - Updated - - - for those of you following this thread,i just confirmed ieee membership not required for publishing
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    [SOLVED] CRC module :- bad synchronous description

    entity crc_v4 is Port ( clk,crc_send,busy : in std_logic; --crc_send is signal to give o/p b_cnt_in : in integer range 0 to 256; --byte count of modbus frame b_cnt_rqs,crc_done,read : out std_logic;--b_cnt_rqs is used to indicate to other module for byte count...
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