Timing simulation in Xilinx

[ajrox]

What is timing simulation?(Xilinx)

Does it reasonably guarantee that the design will work in hardware?

What are steps of Xilinx timing simulation?(should I write a test bench or force values in Isim or ModelSim)

 

[TrickyDicky]

Timing simulation is simultion of the generated netlist with all of the gate delays added. If your timing simulation works, then it is likely to work in real hardware.

You should only resort to timing simulation if you are having problems with the hardware. It is very slow. Do as much debugging as you can in RTL simulation.

 

[std_match]

If you give correct constraints (requirements) to the Xilinx tools, there is normally no need to do a timing simulation.
The tools will automatically do a static timing analysis with margins for temperature, voltage etc, and it will calculate the maximum safe operating frequency.
You have a "reasonable guarantee" that it works if you run the circuit below the maximum frequency.

It is very important to give correct contraints to the tools. If you specify the clock frequency too high, the tools may fail to implement the design. If you specify it too low, the tools can stop optimizing before reaching what you really want.

 

[ajrox]

Thanx TrickyDicky and std_match

I got different results from timing simulation (post place and route) and behavioral simulation.

What could have gone wrong ? ( i did use freq below that of max clock freq)

 

[TrickyDicky]

is your design fully synchronous? The max clock freq has no use in a non-synchronous design. It only measures the best clock frequency between registers, not async logic.

 

[std_match]

I got different results from timing simulation (post place and route) and behavioral simulation.
What could have gone wrong ?

The results after place & route should be correct.
Why bother with timing for behavioral simulation? It will slow down simulations and the timing result will be wrong anyway.
The routing delays affect fMAX, and they are known after place & route.
If your design is synchronous and you get a lower fMAX after place & route, the lower fMAX is probably correct.

 

[mrflibble]

It is very important to give correct contraints to the tools. If you specify the clock frequency too high, the tools may fail to implement the design. If you specify it too low, the tools can stop optimizing before reaching what you really want.

Indeed. Since you say you work with xilinx, have a look at the timing constraints user guide:

https://www.xilinx.com/support/docu...x13_1/ise_n_timing_constraints_user_guide.htm