Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ajayg

  1. A

    How to deal with this DFT warning

    Check your constraints file. May be you have set the shift_enable signal as an ideal network. check for the following string set_ideal_network
  2. A

    how can you interpret qor.rpt from design compiler?

    Hey, IN2OUT is the timing path for Input port to Output port IN2REG is timing path form Input to Register[flop] REG2REG timing path from Register to Register[flop] REG2OUT timing path from Register to Output port. Go through some timing concepts to understand the abv paths. You can find some...
  3. A

    Can't install cadence virtuoso 615 on ubuntu 14.1 64 bit

    Hey if you brought the Cadence Virtuoso 615, it would be better if you approach Cadence Support. AFAIK , Cadence tools require Linux not Ubuntu.
  4. A

    [SOLVED] Threshold Voltage of a MOSFET with channel length 2micron

    You need to mention the target technology to get specific answer.You can simulate the MOSFET in Virtuoso ADE using Spectre Simulator and observe the Vth value in the Result Browser.
  5. A

    Warning for open cell library

    you are using the liberty file which is based on CCS model which is not supported by your tool [RTL Compiler] . Use the liberty files which are based on the NLDM models. This will solve the problem. CCS models are more accurate than NLDM.
  6. A

    PVS rules for gpdk180nm

    in the techRulesets file you need to mention the following lines pvsRuleSet ( "default" ( DrcRules "../DRCdeckfilename" ) ) the path to the DRC deck must be a relative path.
  7. A

    ERC rule check / ERC errors

    Hi mj08, I'm not familiar with atopTech. But , I think the issue could be that the nwell is not biased to VDD (if so u must add an VIA to connect the nwell to VDD ) or it could be that you haven't specified the power pins .
  8. A

    [SOLVED] Difference between PVS and Assura check ?

    Prashanth, Cadence PVS (Physical Verification tool) is an advanced DRC/LVS engine for DRC and LVS check. PVS is specifically for technology nodes below 45nm. Cadence Assura is an older LVS engine which can be used for technology nodes above 45nm.. i.e, 180nm, 130nm.etc., Summary : PVS for...
  9. A

    Dynamic power is reduced when I increased frequency

    Hi, The toggle rates/switching factors used for both cases may be different . If you do not specify the toggle rates, the Synthesis tool will use an estimate toggle factor , for Power estimation. Also check if u have applied the correct timing constraint.
  10. A

    PVS rules for gpdk180nm

    Yathin, the techRuleSets and pvtech.lib files can be created by you..Generally it won't be supplied form the foundry. however you can find the pvlLVS.rul and pvlDRC.rul files in your Cadence Database. For 180nm process, the DRC and LVS rule files will usually be placed in the Assura Directory...
  11. A

    What are these "pink lines" in Cadence schematic editor

    Can u zoom into the pink lines.. there could be some objects at hose points which are connected..
  12. A

    FM Modulator/Demodulator Using Verilog on FPGA

    Hi , As Dan rightly mentioned try to design an NCO and use the message signal to modulate the NCO's output. If u have completed the project by now well and good , else maybe i can help u with it One word of advice though..why did you wait till the deadline? You could have had a better...
  13. A

    Basic difference between RC and DC

    Hi, As Sharath mentioned both tools do the same job but the quality of synthesis differs based on designs. One thing to point is that RC does not perform hold analysis whereas DC has certain options for hold analysis. Also to get more insight you can view the following article...
  14. A

    how to set the library path in cadence virtuoso 6.1.4

    In CIW or cds.log window , go to TOOLS-> lIBRARY pATH EDITOR.._> browse the library folder which u want to add , .after adding the library u need to save it..
  15. A

    [SOLVED] MOSFET model file in cadence folder

    Hi , you can find the nmos and pmos model files in UMC folder which will be present in the cadence folder, it'll be of th .scs extension, open it with some text editor
See more

Part and Inventory Search

Back
Top