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Recent content by aelbad

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    How to extract average data/clock activity from tcf flies?

    Hi, A lot of the time I am conducting power estimation and I have a TCF file for a specific HLB in a design and would like to extract the average data activity [events/cycle] and average clock activity [events/cycle] so that I can make correlation study between power estimation from synthesis...
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    Need your valuable suggestions

    can you provide any tutorial websites or more info on DVT. This actually seems like an interesting approach, that may speed up things :) Thanks :)
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    Best Editor for Verilog Code Navigation

    you may also want to try ultraedit. I recently saw a colleague at work using it and it seems very efficient and very handy on the first glance, that I am considering using it in the future.
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    Best Editor for Verilog Code Navigation

    well when I started I had the same question and the answer i received from my senior colleagues at the time was that whichever editor you start with and get used to, that is the best editor for you. I just prefer emacs because I got used to it. if you want the list of features here is what...
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    Need your valuable suggestions

    Hi, each design is different to verify. you need to brain storm and come up with different testcases for each design. you can look into universal verification methodology in order to get started. simply the ideal checking is to check that all the possible input constellations yield the correct...
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    Best Editor for Verilog Code Navigation

    I like to use emacs which has a lot of features, and it is very powerful once you learn all the shortcut keys and get familiar to it. you can modify and edit large portions of your code using rectangular insert or delete. there are many features which you can take advantage of.
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    [SOLVED] (simple question)Wrapper to set all inputs and output to zero (verilog RTL coding)

    Hi all, can I implement a wrapper which basically only assign all the inputs and outputs to 0 around my already synthesized block using verilog RTL code and synthesis that code into a wrapper around my already synthesized block?:thinker: Thank you, Cheers,
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    [SOLVED] simple question: using verilog can one have an if statment inside a function?

    Thank you everyone for your helpful quick support, I really appreciate it.:thumbsup:
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    [SOLVED] simple question: using verilog can one have an if statment inside a function?

    I am talking about verilog. but still one can use an if statement inside a task as well then why not inside a function? now we have two contradictory replies :D by arishsu and rberek :thinker:
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    [SOLVED] simple question: using verilog can one have an if statment inside a function?

    I just wanted to know if it is not a problem using an if statement inside a function to assign a value to the function output (this should be a simple question :))
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    what are different OTL interface and their corresponding SERDES channels

    I just need to list of Different OTL interface options (i.e OTL4.10) and their corresponding SERDES channels specifications a cheat sheet. Also I would like to know what OTLC2.8 interface corresponds in terms of SERDES channels. Thank you,:thumbsup:
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    [SOLVED] I need support with Synopsys Design Constraints (SDC)

    I found the solution to my problem :) thank you anyway :thumbsup: I just googled and found this which I found to be useful: http://ebook.pldworld.com/_semiconductors/Actel/Libero_v70_fusion_webhelp/sdc_files.htm with a bit of reading on the side, one should be able to put together a good SDC...
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    [SOLVED] I need support with Synopsys Design Constraints (SDC)

    Thank you, I managed to get the SDC file done yesterday by help from a colleague. what do you mean by a solvent account :thinker: I already have in mind to learn on my own :) but still if someone has a quick jump start guide summarizing the main constraints to set common to each design (how to...
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    [SOLVED] I need support with Synopsys Design Constraints (SDC)

    Hi all I am working on designing a small block for the interface of a DAC. I am new to setting SDC constraints. First: For this small block I only need to consider the following constraints in the SDC file and would like the equivalent commands for the SDC file: It should run at a frequency...
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    How could I get gnuplot to graph all the points in the txt file correctly

    I am trying to plot a 3d plot from a data file and I have the following points to plot in my txt file: 0.7 -40 100.4643946 0.7 -20 100.9287892 0.7 0 101.9287892 0.7 25 103.3287892 0.7 40 104.8287892 0.7 70 106.6287892 0.7 85 108.6787892 0.7 100 110.9787892 0.7 125 113.5287892 0.81 -40...
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