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Hi ads-ee,
Thanks for your reply.
The 14-bit data on domain A is parallel and
clock domain B is not derived from domain A.
I have to take the camera input and send it out on the camera link.
So video input from the camera is Domain A and the camera link output is Domain B.
Do I have to use...
I have to read 14 bits of data from clk domain A(7MHz) and write it to a clk domain B(21Mhz).
I'm dealing with video data from camera as the 14 bits as input.
Image resolution is 384x288 and frame rate 50fps.
Output and input frame rates are the same only the clock rates are different.
How do I...
Hi Shibin,
Thanku for the reply.
THe piece of code I'm having problem with is following:
i_data_ddr: ddr_gen
port map
(
Del(3 downto 0) => (others=>'0'),
CLK => clk_out,
Rst => rst,
Data(6 downto 0) => data(6 downto 0),
Q(13 downto 0)...
Hello,
I'm using Lattice ECP2M device with diamond 2.2.
I'm facing with multiple drivers error when connecting the output of ILVDS buffer to the input of a DDR IP component.
HOw can I prevent this?
I read in FIFO datasheet that it needs a continuous clock.So gated clock can't be given directly as input.
Yes I have written test bench and it is in TB I am getting this problem.
Hi,
I am using a gated clock A domain(outside the FPGA) to send data to a clock B domain in FPGA where clock A is slower than clock B.
Here to synchronize the data transmission I have used an asynchronous FIFO .
FIFO write clock is CLKA(generated inside the FPGA and equal to 3*clock A)...
I want to generate 2 channel sine wave and store its samples in ROM using MATLAB.I have to read the samples in the ROM file in verilog code.Can anyone please help me get started with this?
Sorry I thought no one would be interested in going through the whole code.Now I understood writing the whole code only makes sense. New to posting questions thats why.
Code is:
`timescale 1 ns / 1 ps
module adc_bfm;
//Inputs
reg MCLK,RESET_N,SYNC_N;
reg FSI_N,SDI;
reg adc_en...
You are write .It is the problem with initial block.I replaced the function and put it inside always block .Still I have a problem.
My task read starts like this :
task read(input [23:0] Data1,Data2);
begin
Dataout_reg1<=Data1;
Dataout_reg2<=Data2;
....
end
endtask;
It is basically a BFM.The...
I am able to read only the first line in input text file .Can anyone please help me out in debugging this code
In1 and In2 are 32 bit register values and AE is 1 bit binary value.Read is a task inside the testbench which uses file inputs .Code is:
file=$fopen("input.txt","r")...
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