Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
https://datasheets.maximintegrated.com/en/ds/MAX1725-MAX1726.pdf
I am modeling LDO of MAX1762.
Initially I set W, L, Kp value according to Ron required but I didnt obtain dropout voltage required. So I added 9.4 ohm series resistance. Then by trial and error method i set gain of Error...
I have set Rds on of LDO using model card
I have obtained 178mOhm Now i have to use in LDO as pass transistor can i directly use this so that Ron will be the same for dropout test case? How should I move forward in developing LDO simple control loop (Pass element, EA , Feedback divider)...
I am modeling SAR ADC from scratch I am going through TI precision instruments adc videos. Here they have mentioned in 9:25 they have assumed Ref capacitive load as Csh/4 and carried conversion cycles. I am not able to relate this with actual CDAC capacitor redistribution process. How to...
I am in the journey of understanding operation of data converters and in mean time I found SAR ADC fascinating. I have a question regarding charge redistribution DAC as given in this document
But TI slide 4 and 5 of this link provides different view CDAC block has comparator with positive...
I am modeling LDO in PSpice, here i have selected spec as ZXCL280 in dropout vs output current I have understood this as resistance of the MOSFET from dropout graph. That is minimum resistance required for the MOSFET, 2 OHMS (Page No 4). I will be using Ron=1/kp(Vgs-vt)...
I am trying to understand compensation using TPS40200 https://www.ti.com/lit/ds/symlink/tps40200.pdf, the flow is given in Page 26 to 30 of the document.
This sentence is bit is irrelevant in Page 29, because Kfb feedback gain is already calculated previously as 11.4dB the only remaining factor...
I am trying to model behavior of UC3842 PWM controller https://www.ti.com/lit/ds/symlink/uc3842.pdf
By information from the datasheet done a crude model of loop behavior, But as you can see I have not used error amplifier or without matching the open loop gain given in datasheet If I change any...
I am curious to understand Analog-Digital Interface Bridge in SiMetrix which has model card with these parameters as mentioned in image
I am simulating this component with this test setup
Simulation waveform
in_low=2.1
in_high=2.2
which can be understood as thresholds but looks like...
https://www.ti.com/lit/ds/symlink/lm5102.pdf
This gives IDD vs Frequency plot at page no:7 for different Load Capacitor (CL)
How is this plot (Figure no:1) measured/Test Setup on EVM Board (Characterized) and Design Simulation Plot ?
@FvM 2*Fswitch*Qg,total + LM5102 quiescent current gives - 2*500KHz*43nC(assume)+0.4mA this gives huge value...
https://imgur.com/a/Lhe7gDc
This is the current behavior which i obtain at VDD when input is 500KHz at low side even after i use capacitor at VDD and GND
I have measured operating current at VDD referring application circuit in datasheet. (With condition f=500khz) Whenever there is raising input pulse I observe a current spike at VDD and during falling.
May I know the formula for calculating the average current here and is it dependent on duty...
I am understanding the datasheet parameters of LM5102. I am not understanding how is operating current measured (average / RMS current ) conditions is given as f=500khz in electrical characteristics
Can any one share some insights on these?
Datasheet: http://www.ti.com/lit/gpn/lm5102
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
