Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ackqin

  1. A

    how can I improve FIFO timing?

    echo47, thanks. I use xc3s400 -4, I only use this fifo in FPGA, all the signal is in the fpga. This fifo saves my data, and I will read out when I need. so I want to know, but the data out speed of fifo can't satisfy my 125Mhz requirement, so I want to know is there any way can make the data...
  2. A

    how can I improve FIFO timing?

    fifo timing I use SPARTANIII internal block ram as FIFO, but the timing can't satisfy my requirement, the detail is as below: I need 125Mhz speed, but the ram data out can only implement about 100Mhz, how can I improve the speed. thanks, ackqin Timing constraint: TS_lclk = PERIOD TIMEGRP...
  3. A

    which download file should I use?

    thanks you echo47. I have successfully download it. bit and bin file all can do, I send the MSB(bit 7) first. Later I find bit file is mostly same as bin file, only differ in some title information which is no use for FPGA, it seek 4 FF to start data write, the title information will be ignored.
  4. A

    which download file should I use?

    I am doing a project using ARM9, I also want to use ARM9 and AMD 16 bit flash configuring FPGA(spartan3 xc3s400), I use serial slave mode, ARM9 get parallel data and I send it out by serial. but I dont know which file should I use to download the FPGA, bin or bit or mcs or others? also which bit...
  5. A

    how to implement EDF with ram instantiation in ISE

    I synthesize my project in synplicity, then I use the edf file to place&route, but I meet error, because I used several block ram in the code. how can I solve this problem. I use ISE and SPRARTAN3 XC3S400 THANKS ackqin
  6. A

    how to deal the path who can't satisfy timing constraints?

    Re: how to deal the path who can't satisfy timing constraint hi wadaye, thanks for your advice. but how can I make my synthesize effort? ackqin
  7. A

    how to deal the path who can't satisfy timing constraints?

    can I ref the frequency XST synthesize result? everytime after synthesize, xst will give a reference frequency, it's so low, but in my timing report, I can see the period constraint is satisfied. and this period is more higher than the xst result, I am puzzled whether this xst frequency is...
  8. A

    how to deal the path who can't satisfy timing constraints?

    I only add period and offset on my code, but there is one path don't satisfy the period constraints, and several path don't satisfy the offset out constraints. I don't know how to deal with it. can anybody give me some advice? I use spartan3, ise7.1 thanks a lot ackqin
  9. A

    how can I get best constraint result.

    I am doing a project, the running frequency is not satisfied. so I tried to add some timing constraints to it, but I don't know whether I should add it on synplify or ise using UCF. also I have a lot puzzle about timing constraint, how can I recognize the critical path in ise, is there some...
See more

Part and Inventory Search

Back
Top