Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how can I get best constraint result.

Status
Not open for further replies.

ackqin

Newbie level 5
Joined
Nov 15, 2005
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,376
I am doing a project, the running frequency is not satisfied. so I tried to add some timing constraints to it, but I don't know whether I should add it on synplify or ise using UCF. also I have a lot puzzle about timing constraint, how can I recognize the critical path in ise, is there some document about this issue? Can anybody give the address.

Thanks a lot.

ackqin
 

After synthesis of ISE, you can see the critical path from the report.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top