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Recent content by Abdo18

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    Reading layout file in SoC Encounter

    I'm not an analog design engineer, so please if you know just tell me.
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    Reading layout file in SoC Encounter

    In which view should the DEF file generated in Virtuoso: layout, schematic or abstract view?
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    Reading layout file in SoC Encounter

    The DEF file generated by Virtuoso doesn't contain any information about the design. It's between 10 and 20 lines only.
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    Effect of doubling via cuts on the parasitics

    If I doubled the number of all via cuts in my design, how could this affect the resistance and capacitance, thus I know how it affects timing?
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    Reading layout file in SoC Encounter

    The analog design engineer made some modifications on the design layout in Cadence Virtuoso, and he wants me to check timing of the digital core in the modified design using SoC encounter. What file can he generate that I can read?
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    [SOLVED] Logical and physical 0.13 or 0.18 um technology library

    I'm working on a project and now I'm in the PnR phase using Synopsys IC Compiler tool. but I need a free source to get both logical and physical library files of 0.18 or 0.13um tech node
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