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Recent content by abcyin

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    How to define opamp specs within an active-RC filter

    Thanks for all of you, the suggestions are constructive. I'll come back to the discussion after reading the documents. Thanks.
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    How to define opamp specs within an active-RC filter

    Hi, all, If we have to design an active-RC filter with some specs given, such as cut-off frequency, SFDR, and load, then how to define the opamp specs (GBW, slew rate, rin, rout)? It would be appreciated if any of you could provide some literatures on this topic. Thanks in advance, abcyin
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    How could the transmitter gain loss in measurement?

    Hi, all, The TX is designed to be with 5dB gain from analog baseband to RF sections, but it turns out to be -5dB, while the trace loss and cable loss have been considered. that's to say, there are 10dB difference between simulation and measurement. I could not figure out that how could this...
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    Question on simulating LO leakage for a transmitter

    the mismatch process is included in the simulation by selecting the mc process corner of the model, I could get some worst case with 40dB leakage by montecarlo simulation. And the LO is generated by a divider /2, only 0 and 180 phase is selected and transmitted as we use BPSK modulation...
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    Question on simulating LO leakage for a transmitter

    Thanks for your reply, the spec for LO rejection is larger than -30dBc, thus I'm expecting a 40dBc from the simulation. The TX is a BPSK modulation without IQ, the LO phase is selected by the baseband digital signals, thus I think DC offset at IF is the main cause for LO leakage. what do you...
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    Question on simulating LO leakage for a transmitter

    Thanks for your reply, The simulation is with layout parasitics and mismatch is also included, the simulation shows that a -50dB LO rejection could be achieved, while turns out to be -20 after measurement. abcyin
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    Question on simulating LO leakage for a transmitter

    Dear all, I am wondering how to simulate the LO leakage of a transmitter, I tried transient and DFT to get the spectrum, while the results are too far away from the measurement. so could anyone tell me how to simulate such performance, by which analysis. Thanks in advance, abcyin
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    LVS error on transistor size mismatch

    Thank you all, I solved this problem by changing trace property in the LVS rule.
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    LVS error on transistor size mismatch

    Thanks for your kind reply, the error is actually due to the mosfets in std cells, but could you pls tell me how to increase the tolerance, do you mean I have to modify the rule file, but how to?
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    LVS error on transistor size mismatch

    Hi, all, I got some error when I run LVS check, the transistor size extracted from layout is very close to the size from the schematic, but they are actually different with number of fractions, as shown in the following figure, could anyone tell me how to solve this problem, thanks in advance!
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    Question on simulating Quadrature Mixer

    Hi, all, I am trying to simulate the OIP3 of the quadrature mixer, and I found that if I set the LO of the quadrature mixer to be 90 degree apart, that's quadrature LO input to the mixer, then the output OIP3 of the two mixers' output would be different, about 3dB difference, by QPSS analysis...
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    Question on Modeling multiple ground regions with mentor calibre

    Thanks very much for your kind reply, I am using Calibre PEX to extract the parasitics, I am not sure about how to "mark the regions and add those layers to the CONNECT statement" as you said. For example in my layout, there are two grounds named GND_1 and GND_2, should I use the CONNECT...
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    Question on Modeling multiple ground regions with mentor calibre

    Hi, all, I'd like to analyse the substrate noise coupling with mentor calibre, which supports this function as "modeling multiple ground regions", but the calibre user manual doesn't tell me how to make it, so could anyone has this kind of experience on how to extract this parasitics with this...
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    Question on ESD discharge current path?

    Hi, all, A question arises when I'm designing the ESD circuit. you know there are some modes when you're testing the ESD circuits, among which the ESD stress between VDD and VSS should be checked. what I'd like to know is how the discharge current flows when a negative impluse occures at the...
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    Filter in transmitter

    Hi, LvW, Thanks for your reply. Actually, the attenuation is a range, like -20dB to -3dB, why it's so important as you said?
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