LVS error on transistor size mismatch

[abcyin]

Hi, all,

I got some error when I run LVS check, the transistor size extracted from layout is very close to the size from the schematic, but they are actually different with number of fractions, as shown in the following figure, could anyone tell me how to solve this problem, thanks in advance!

 

[dgnani]

Hi abcyin

This can happen under various circumstances most typically when there is a jog on the gate (45deg turns) used in commercial std cells to increase density.

The simplest option is to ignore it or better verify that these little violations are not masking important ones by temporarily increasing the tolerance (see TRACE PROPERTY command in calibre manual)

 

[abcyin]

Hi abcyin

This can happen under various circumstances most typically when there is a jog on the gate (45deg turns) used in commercial std cells to increase density.

The simplest option is to ignore it or better verify that these little violations are not masking important ones by temporarily increasing the tolerance (see TRACE PROPERTY command in calibre manual)

Thanks for your kind reply, the error is actually due to the mosfets in std cells, but could you pls tell me how to increase the tolerance, do you mean I have to modify the rule file, but how to?

 

[dgnani]

There are various options to achieve that depending on how the rule file is set up:
- you might simply have to define or redefine an internal calibre variable
- you might have to add SVRF commands in the inlude section
- you might have to change the rule file

In any case you'll have to look that up in Calibre manual under TRACE PROPERTY

 

[erikl]

... could you pls tell me how to increase the tolerance, do you mean I have to modify the rule file, but how to?

You didn't reveal your LVS tool. In diva (resp. assura) special procedures were used, e.g. see below:

procedure(compareMOS(layMos schMos)
  prog(nil
    unless( and(layMos->w schMos->w layMos->l schMos->l)
      sprintf(errorC
	  "Nil parameter: w:%g l:%g (layout) w:%g l:%g (schematic)"
          layMos->w layMos->l schMos->w schMos->l)
          return(errorC)
    )

    when(abs(layMos->w - schMos->w * schMos->m) > 0.01 * schMos->w * schMos->m
    && abs(layMos->l - schMos->l) > 0.001 * schMos->l
        sprintf(errorwl
	    "Gate w & l mismatch : total w:%g l:%g (layout) w:%g m:%g l:%g (schematic)"
        float(layMos->w) float(layMos->l)
        float(schMos->w) float(schMos->m) float(schMos->l)) 
        return(errorwl)
    )
    when(abs(layMos->w - schMos->w * schMos->m) > 0.01 * schMos->w * schMos->m
        sprintf(errorw "Gate w mismatch: total w:%g (layout) w:%g m:%g (schematic)"
        float(layMos->w) float(schMos->w) float(schMos->m) )
        return(errorw)
    )
    when(abs(layMos->l - schMos->l) > 0.001 * schMos->l
        sprintf(errorl
	"Gate length mismatch: %g layout to %g schematic"
        float(layMos->l) float(schMos->l))
        return(errorl)
    )
    return(nil)

 

[dgnani]

Hi erikl

The tool is clearly MGC Calibre

I just cannot solve his problem w/o making sure he owns a manual...

 

[dick_freebird]

There may be (have seen, in other tools' decks) a tolerance you
can specify either globally or per-rule (although you might not
be given access to the run-set, you may be able to edit a copy).

Alternatively, change your schematic to what the layout extract
is claiming to find; if the W:W difference is as trivial as you claim,
then that should not hurt anything.

 

[abcyin]

Thank you all, I solved this problem by changing trace property in the LVS rule.