Zero delay for interconnects in SDF file of Design Compiler

[shm]

Hello all,
I used Design Compiler to generate .sdf file for my design; I used wire-load standard models.
As I see through my generated sdf file, there is not any timing(delay) report on my interconnects (all are set to 0)!! LIKE:

(INTERCONNECT U26245/Y U26248/A (0.000:0.000:0.000))
(INTERCONNECT U4068/Y U26247/A0 (0.000:0.000:0.000))
(INTERCONNECT U26245/Y U26247/A1N (0.000:0.000:0.000))
(INTERCONNECT U26248/Y U26247/B0 (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26247/B1N (0.000:0.000:0.000))
(INTERCONNECT U23544/Y U26246/A (0.000:0.000:0.000))
(INTERCONNECT ai8\/U87/Y U26246/B (0.000:0.000:0.000))
(INTERCONNECT U23300/Y U26245/A (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26245/B (0.000:0.000:0.000))
(INTERCONNECT U26242/Y U26244/A (0.000:0.000:0.000))

Is this OK? the sdf files with wire-load models should not have any delay in interconnects on top module!?
Then, what is the wire-load libraries for (where do their models would put their effects on our circuits -especially on our hold and setup time-)?
Why we should use "set_wire_load_model" in Design Compiler scripts?

 

[jeet_asic]

Wht is your design basically? give some details . Having Zero delays is undigestable . No matter what your setting are , you are bound to get atleast some delay .

Wire load models define nets length with number of fanouts at different PTV conditions . As you increase fanouts , length of fanout also increase. If you do " man set_wire_load_manual" you will get each and every detail in DC . If you have used wire load models , then you should get some amount of delays.

Use " report_timing" and check out detailed report.

 

[rca]

This cell are related to clock net or data net?
Remember where you apply the create_clock, if there is no timing arc at is output, the complete net is considered as ideal.

 

[shm]

Thank you,
My design is about a simple LFSR, but as I search through my .sdf file, I find it that DC has not considered any delay for my interconnects, but my cells have their delays and it has been reported in the sdf file. I should add that, I have considered the input and output delays and their Fan-Outs.