shm
Newbie level 4
Hello all,
I used Design Compiler to generate .sdf file for my design; I used wire-load standard models.
As I see through my generated sdf file, there is not any timing(delay) report on my interconnects (all are set to 0)!! LIKE:
(INTERCONNECT U26245/Y U26248/A (0.000:0.000:0.000))
(INTERCONNECT U4068/Y U26247/A0 (0.000:0.000:0.000))
(INTERCONNECT U26245/Y U26247/A1N (0.000:0.000:0.000))
(INTERCONNECT U26248/Y U26247/B0 (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26247/B1N (0.000:0.000:0.000))
(INTERCONNECT U23544/Y U26246/A (0.000:0.000:0.000))
(INTERCONNECT ai8\/U87/Y U26246/B (0.000:0.000:0.000))
(INTERCONNECT U23300/Y U26245/A (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26245/B (0.000:0.000:0.000))
(INTERCONNECT U26242/Y U26244/A (0.000:0.000:0.000))
Is this OK? the sdf files with wire-load models should not have any delay in interconnects on top module!?
Then, what is the wire-load libraries for (where do their models would put their effects on our circuits -especially on our hold and setup time-)?
Why we should use "set_wire_load_model" in Design Compiler scripts?
I used Design Compiler to generate .sdf file for my design; I used wire-load standard models.
As I see through my generated sdf file, there is not any timing(delay) report on my interconnects (all are set to 0)!! LIKE:
(INTERCONNECT U26245/Y U26248/A (0.000:0.000:0.000))
(INTERCONNECT U4068/Y U26247/A0 (0.000:0.000:0.000))
(INTERCONNECT U26245/Y U26247/A1N (0.000:0.000:0.000))
(INTERCONNECT U26248/Y U26247/B0 (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26247/B1N (0.000:0.000:0.000))
(INTERCONNECT U23544/Y U26246/A (0.000:0.000:0.000))
(INTERCONNECT ai8\/U87/Y U26246/B (0.000:0.000:0.000))
(INTERCONNECT U23300/Y U26245/A (0.000:0.000:0.000))
(INTERCONNECT ai2\/U52/Y U26245/B (0.000:0.000:0.000))
(INTERCONNECT U26242/Y U26244/A (0.000:0.000:0.000))
Is this OK? the sdf files with wire-load models should not have any delay in interconnects on top module!?
Then, what is the wire-load libraries for (where do their models would put their effects on our circuits -especially on our hold and setup time-)?
Why we should use "set_wire_load_model" in Design Compiler scripts?